Designing FPGAs Using the Vivado Design Suite 3

Course Description

Learn how to effectively employ timing closure techniques.
This course includes:

  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design

 

 

PrintLevel

FPGA 3

Course Duration

2 days

Audience

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite

Prerequisites

Software Tools

  • Vivado Design Suite  2023.1

Hardware

  • Architecture: UltraScale FPGAs*
  • Demo board board: Zynq® UltraScale+™ ZCU104 board*

*This course focuses on the UltraScale architectures. Check with your local Authorized Training Provider for the specifics of the inclass lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems. and requires less design debugging later in the development cycle
  • Implement Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
  • Perform quality of results (QoR) assessments at different stages to improve the QoR score
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Describe how to enable remote debug

Course Outline

Day 1

  • UltraFast Design Methodology Implementation – Introduces the methodology guidelines covered in this course. {Lecture}
  • Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware. {Lecture, Lab}
  • Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Demo, Lab}
  • Pipelining – Use pipelining to improve design performance. {Lecture, Lab}
  • Inference – Infer xilinx dedicated hardware resources by writing appropriate HDL code. {Lecture, Lab}
  • I/O Timing ScenariosProvides an overview of various I/O timing scenarios, such as source and systemsynchronous, direct/MMCM capture, and edge/centeraligned data. {Lecture}
  • SystemSynchronous I/O TimingDemonstrates applying I/O delay constraints and performing static timing analysis for a systemsynchronous input interface. {Lecture, Demo}
  • SourceSynchronous I/O TimingDemonstrates applying I/O delay constraints and performing static timing analysis for a sourcesynchronous, double data rate (DDR) interface.  Lecture, Lab}
  • Timing Constraints Priority – Reviews how to identify the priority of timing constraints. {Lecture}
  • Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains. {Lecture, Demo}
  • Report Data Sheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface. {Lecture, Demo}
  • Report QoR – Use the QoR Assessment and QoR Suggestions reports to analyze the timing for a design. {Lecture, La

Day 2

  • Sampling and Capturing Data in Multiple Clock Domains – Overview of debugging a design with multiple clock domains that require multiple ILAs. {Lecture, Lab}
  • Clock Domain Crossing (CDC) and Synchronization Circuits – Use synchronization circuits for clock domain crossings. {Lecture, Lab, Case Study}
  • Revision Control Systems in the Vivado Design SuiteInvestigates using version control systems with the Vivado design flows. {Lecture, Lab}
  • Dynamic Power Estimation Using Vivado Report Power.– Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design. {Lecture, Lab}
  • Configuration Modes – Understand various configuration modes and select the suitable mode for a design. {Lecture}
  • Netlist Insertion Debug Probing Flow – Covers the netlist insertion flow of the debug using the Vivado logic analyzer {Lecture, Lab}
  • JTAG-to-AXI-Master Core. – Use this debug core to write/read data to/from a peripheral connected to an AXI interface. {Lecture, Lab}
  • Debug Flow in an IP Integrator Block Design – Insert the debug cores into IP integrator block designs. {Lecture, Lab}
  • Remote Debugging Using the Vivado Logic Analyzer.– Use the Vivado logic analyzer to configure an FPGA, set up triggering,.and view the sampled data from a remote location. {Lecture, Lab}.
  • Design Analysis Using Tcl CommandsDescribes how to analyze a design using Tcl commands. {Lecture, Demo}

 

 

FPGA


Datum
08 april 2024 - 09 april 2024

Locatie
Core|Vision
Cereslaan 24
5384 VT
Heesch

Prijs
€ 2.000,00
of
20 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

Tickets

FPGA VDES3

€ 2.000,00

Registratiegegevens

Booking Summary

1
x Standaardticket
€ 2.000,00
Totale Prijs
€ 2.000,00