Designing FPGAs Using the Vivado Design Suite 1

Course Description

This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.

The course provides experience with:

  • Creating a Vivado Design Suite project with source files
  • Simulating a design
  • Performing pin assignments
  • Applying basic timing constraints
  • Synthesizing and implementing
  • Debugging a design
  • Generating and downloading a bitstream onto a demo board

PrintLevel

FPGA 1

Course Duration

2 days

Audience

Digital designers new to FPGA design who need to learn the FPGA design.cycle and the major aspects of the Vivado Design Suite

Prerequisites

  • Basic knowledge of the VHDL or Verilog language
  • Digital design knowledge

Software Tools

  • Vivado Design Suite 2023.2

Hardware

  • Architecture: UltraScale™ FPGAs*
  • Demo board (optional): Zynq UltraScale+ ZCU104 board*

* This course focuses on the UltraScale  architectures. Check with your local Authorized Training Provider for the specifics of the inclass lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the New Project Wizard to create a new Vivado IDE project
  • Describe the supported design flows of the Vivado IDE
  • Generate a DRC report to detect and fix design issues early in the flow
  • Use the Vivado IDE I/O Planning layout to perform pin assignments
  • Perform clocking and static timing analysis (STA)
  • Synthesize and implement the HDL design
  • Apply clock and I/O timing constraints and perform timing analysis
  • Use the Xilinx Power Estimator (XPE) tool to estimate power
  • Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
  • Use the Vivado logic analyzer and debug flows to debug a design

Course Outline

Day 1

  • Introduction to FPGAs Provides an overview of FPGA architecture and describes the advantages, applications, and major building blocks of FPGAs. {Lecture}
  • AMD FPGA & Adaptive SoC Families Introduces 7 series and UltraScale FPGAs, stacked silicon interconnectbased 3D IC devices, Zynq®7000 SoCs, Zynq UltraScale+ MPSoCs, and Versal™ adaptive SoCs. {Lecture}
  • Introduction to the Vivado Design SuiteDescribes various design flows and the role of the Vivado IDE in the flow. {Lecture}
  • Introduction to the Tcl Environment Introduces Tcl (tool command language). {Lecture}
  • Vivado Design Suite ProjectBased ModeIntroduces projectbased mode in the Vivado Design Suite, including creating a project, adding files to a project, exploring the Vivado IDE, and simulating a design. {Lecture, Lab}
  • Vivado Design Suite NonProject Based ModeDescribes the design flow using nonproject batch mode, including using design analysis commands and how constraints are managed in nonproject mode. {Lecture}
  • UltraFast Design Methodology: Board and Device Planning –Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. {Lecture}
  • RTL DevelopmentCovers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets. {Lecture}
  • Behavioral SimulationDescribes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}
  • Vivado IP FlowDemonstrates how to customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab}
  • Vivado Synthesis and Implementation and Bitstream GenerationReviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board. {Lecture, Lab}
  • Basic Design Analysis in the Vivado IDE – Outlines the various design analysis features in the Vivado Design Suite. {Demo, Lab}
  • Vivado Design Rule Checks – Illustrates how to run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab}
  • Introduction to Vivado Reports – Demonstrates generating and using Vivado timing reports to analyze failed timing paths. {Lecture, Demo}

Day 2

  • Introduction to Clock ConstraintsShows how to apply clock constraints and perform timing analysis. {Lecture, Demo, Lab}
  • Generated ClocksDemonstrates using the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo}
  • I/O Constraints and Virtual ClocksCovers applying I/O constraints and performing timing analysis. {Lecture, Lab}
  • Timing Constraints WizardReviews how use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}
  • Static Timing Analysis (STA)Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}
  • Setup and Hold Violation AnalysisCovers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}
  • Vivado Design Suite I/O Pin Planning – Describes the I/O Pin Planning layout for performing pin assignments in a design. {Lecture, Lab}
  • Power Estimation Using XPEIllustrates estimating the amount of resources and default activity rates for a design and evaluating the estimated power calculated by XPE. {Lecture, Lab}
  • Understanding Power for Better Time to Market Describes the importance of power closure and device selection for better time to market. {Lecture}
  • Versal ACAP: Power Design Manager Discusses using the Power Design Manager tool, including import and export functions.
  • Introduction to FPGA ConfigurationDescribes how FPGAs can be configured. {Lecture}
  • Introduction to the Vivado Logic AnalyzerProvides an overview of the Vivado logic analyzer for debugging a design. {Lecture, Demo}
  • Introduction to TriggeringIntroduces the trigger capabilities of the Vivado logic analyzer. {Lecture}
  • Debug CoresDescribes how the debug hub core is used to connect debug cores in a design. {Lecture}

 

FPGA


Datum
08 april 2024 - 09 april 2024

Locatie
Core|Vision
Cereslaan 24
5384 VT
Heesch

Prijs
€ 2.000,00
of
20 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

Tickets

FPGA VDES1

€ 2.000,00

Registratiegegevens

Booking Summary

1
x Standaardticket
€ 2.000,00
Totale Prijs
€ 2.000,00