Core|Vision biedt FPGA trainingen, zoals aangegeven in het trainingsschema hieronder. Staat uw gewenste training er niet bij of past de datum niet in uw agenda? Neem dan contact op met Core|Vision om te bespreken hoe we dit kunnen aanpassen aan uw behoeften.
✅ GAAT DOOR
februari - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
10
|
Embedded | Migrating to the Vitis Embedded Software Development IDE Workshop | Heesch |
-
|
|
10
|
Doulos | Formal Verification for Non-Specialists ✅ | Webinar | |
|
13 - 14
|
Connectivity | Designing with Xilinx Serial Transceivers | Heesch |
-
|
|
13 - 14
|
DSP | Essential DSP Implementation Techniques for Xilinx FPGAs | Heesch |
-
|
|
15
|
Doulos | Deep Learning with FPGAs ✅ | Webinar | |
|
16 - 17
|
ACAP | Design Closure Techniques ✅ | Heesch |
-
|
|
16 - 17
|
AI | Developing AI Inference Solutions with the Vitis AI Platform | Heesch |
-
|
|
17
|
Doulos | Bare Metal or RTOS? The answer is not as you might think ... ✅ | Webinar | |
|
20 - 21
|
DSP | High-Level Synthesis with the Vitis HLS Tool | Heesch |
€ 2.000,00
|
|
22
|
Doulos | Edge Machine Learning - Project Tips & Tricks ✅ | Webinar | |
|
23 - 24
|
FPGA | Workshop: Spartan-6 Migration to 7 series or UltraScale+ (PST timezone) ✅ | Online |
-
|
|
23 - 24
|
FPGA | Workshop: Spartan-6 Migration to 7 series or UltraScale+ (CET timezone) ✅ | Online |
-
|
|
24
|
Doulos | Clock Domain Crossing ✅ | Webinar |
maart - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
07 - 08
|
ACAP | Designing with Versal AI Engine: Architecture and Design Flow (1) | Heesch |
€ 2.000,00
|
|
09 - 10
|
ACAP | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) | Heesch |
€ 2.000,00
|
|
13 - 14
|
Digital Design | Essential Digital Design Techniques | Heesch |
€ 2.050,00
|
|
13 - 14
|
Doulos | Essential Tcl | Heesch |
€ 2.050,00
|
|
16 - 17
|
DSP | DSP Design Using System Generator | Heesch |
€ 2.000,00
|
|
16 - 17
|
DSP | Vitis Model Composer: A MATLAB and Simulink-based Product | Heesch |
€ 2.000,00
|
|
20 - 21
|
ACAP | Design Closure Techniques | Heesch |
€ 2.000,00
|
|
20 - 21
|
Embedded | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite | Heesch |
€ 2.000,00
|
|
27 - 29
|
ACAP | Accelerating Applications with the Vitis Unified Software Environment | Heesch |
€ 3.000,00
|
april - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
03 - 07
|
Doulos | Expert VHDL | Heesch |
€ 4.350,00
|
|
03 - 04
|
Doulos | Expert VHDL Design | Heesch |
€ 2.195,00
|
|
05 - 07
|
Doulos | Expert VHDL Verification | Heesch |
€ 3.095,00
|
|
11 - 12
|
FPGA | Designing with the UltraScale and UltraScale+ Architectures | Heesch |
€ 2.000,00
|
|
11 - 12
|
FPGA | UltraFast Design Methodology | Heesch |
€ 2.000,00
|
|
13 - 14
|
Connectivity | Designing with Xilinx Serial Transceivers | Heesch |
€ 2.000,00
|
|
13 - 14
|
Embedded | Zynq All Programmable SoC System Architecture | Heesch |
€ 2.000,00
|
|
17 - 21
|
Doulos | Comprehensive VHDL | Heesch |
€ 4.095,00
|
|
17 - 19
|
Doulos | VHDL for Designers | Heesch |
€ 2.995,00
|
|
20 - 21
|
Doulos | Advanced VHDL | Heesch |
€ 2.050,00
|
|
25 - 26
|
DSP | Essential DSP Implementation Techniques for Xilinx FPGAs | Heesch |
€ 2.000,00
|
|
25 - 26
|
Embedded | Zynq UltraScale+ MPSoC for the Hardware Designer | Heesch |
€ 2.000,00
|
|
28
|
ACAP | Designing with the IP Integrator Tool | Heesch |
€ 1.000,00
|
mei - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
01 - 02
|
FPGA | Designing FPGAs Using the Vivado Design Suite 1 | Heesch |
€ 2.000,00
|
|
01 - 02
|
Embedded | Embedded Systems Design | Heesch |
€ 2.000,00
|
|
03 - 04
|
FPGA | Designing FPGAs Using the Vivado Design Suite 2 | Heesch |
€ 2.000,00
|
|
03 - 05
|
Embedded | Embedded Systems Software Design | Heesch |
€ 3.000,00
|
|
08 - 09
|
FPGA | Designing FPGAs Using the Vivado Design Suite 3 | Heesch |
€ 2.000,00
|
|
08 - 09
|
DSP | High-Level Synthesis with the Vitis HLS Tool | Heesch |
€ 2.000,00
|
|
10 - 11
|
FPGA | Designing FPGAs Using the Vivado Design Suite 4 | Heesch |
€ 2.000,00
|
|
10 - 11
|
Embedded | Zynq UltraScale+ MPSoC for the Hardware Designer | Heesch |
€ 2.000,00
|
|
15 - 16
|
DSP | DSP Design Using System Generator | Heesch |
€ 2.000,00
|
|
15 - 16
|
DSP | Vitis Model Composer: A MATLAB and Simulink-based Product | Heesch |
€ 2.000,00
|
juni - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
12 - 14
|
ACAP | Designing with the Versal ACAP: Architecture and Methodology | Heesch |
€ 3.000,00
|
|
15
|
ACAP | Designing with the Versal ACAP: Network on Chip | Heesch |
€ 1.000,00
|
|
15 - 16
|
ACAP | Designing with Versal AI Engine: Architecture and Design Flow (1) | Heesch |
€ 2.000,00
|
|
19 - 20
|
ACAP | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) | Heesch |
€ 2.000,00
|
|
19 - 20
|
Digital Design | Essential Digital Design Techniques | Heesch |
€ 2.050,00
|
|
21 - 23
|
ACAP | Accelerating Applications with the Vitis Unified Software Environment | Heesch |
€ 3.000,00
|
|
26 - 30
|
Doulos | Expert VHDL | Heesch |
€ 4.350,00
|
|
26 - 27
|
Doulos | Expert VHDL Design | Heesch |
€ 2.195,00
|
|
28 - 30
|
Doulos | Expert VHDL Verification | Heesch |
€ 3.095,00
|
juli - 2023
| Datum | Categorie | Training | Locatie | Prijs |
|---|---|---|---|---|
|
03 - 04
|
Doulos | Essential Tcl | Heesch |
€ 2.050,00
|
|
10 - 14
|
Doulos | Comprehensive VHDL | Heesch |
€ 4.095,00
|
|
10 - 12
|
Doulos | VHDL for Designers | Heesch |
€ 2.995,00
|
|
13 - 14
|
Doulos | Advanced VHDL | Heesch |
€ 2.050,00
|