Aankomende Evenementen
- Vitis Model Composer: A MATLAB and Simulink-based Product - 07/12/2023 - 08/12/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 08/12/2023 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 11/12/2023 - 12/12/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 13/12/2023 - 15/12/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 18/12/2023 - 19/12/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 20/12/2023 - 21/12/2023 - 09:00 - 17:00
- Embedded Systems Software Design - 21/12/2023 - 22/12/2023 - 09:00 - 17:00
- Design Closure Techniques ✅ - 09/01/2024 - 10/01/2024 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 4 - 02/01/2050 - 12:00 - 20:00
- Vivado Design Suite for ISE Software Project Navigator Users - 03/01/2050 - 09:00 - 17:00
- Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users - 03/01/2050 - 10:00 - 18:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00
- Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite - 05/01/2050 - 10:00 - 18:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 07/01/2050 - 09:00 - 17:00
- DSP Design Using System Generator - 07/01/2050 - 10:00 - 18:00