Aankomende Evenementen
- High-Level Synthesis with the Vitis Unified IDE - 06/05/2024 - 07/05/2024 - 09:00 - 17:00
- Adaptive SoCs for System Architects - 13/05/2024 - 14/05/2024 - 09:00 - 17:00
- Embedded Systems Design - 13/05/2024 - 14/05/2024 - 09:00 - 17:00
- Embedded Systems Software Design - 15/05/2024 - 17/05/2024 - 09:00 - 17:00
- Operating Systems and Hypervisors in Adaptive SoCs - 15/05/2024 - 17/05/2024 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit & System-on-Module - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Design Closure Techniques - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 4 - 02/01/2050 - 12:00 - 20:00
- Vivado Design Suite for ISE Software Project Navigator Users - 03/01/2050 - 09:00 - 17:00
- Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users - 03/01/2050 - 10:00 - 18:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00
- Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite - 05/01/2050 - 10:00 - 18:00