Aankomende Evenementen
- Designing with the Versal ACAP: Architecture and Methodology - 19/06/2023 - 21/06/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 22/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 22/06/2023 - 23/06/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 26/06/2023 - 28/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 29/06/2023 - 30/06/2023 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 29/06/2023 - 30/06/2023 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 05/07/2023 - 06/07/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 1 - 14/08/2023 - 15/08/2023 - 09:00 - 17:00
- Embedded Systems Design - 14/08/2023 - 15/08/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 16/08/2023 - 17/08/2023 - 09:00 - 17:00
- Embedded Systems Software Design - 16/08/2023 - 18/08/2023 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 18/08/2023 - 09:00 - 17:00
- Design Closure Techniques - 21/08/2023 - 22/08/2023 - 09:00 - 17:00
- UltraFast Design Methodology - 21/08/2023 - 22/08/2023 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 23/08/2023 - 24/08/2023 - 09:00 - 17:00
- High-Level Synthesis with the Vitis HLS Tool - 23/08/2023 - 24/08/2023 - 09:00 - 17:00
- Adaptive SoCs for System Architects - 28/08/2023 - 29/08/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 3 - 28/08/2023 - 29/08/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 4 - 30/08/2023 - 31/08/2023 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 30/08/2023 - 31/08/2023 - 09:00 - 17:00