Aankomende Evenementen
- Designing with the Versal ACAP: Network on Chip - 03/02/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 3 - 06/02/2023 - 07/02/2023 - 09:00 - 17:00
- Zynq UltraScale+ MPSoC for the System Architect - 06/02/2023 - 07/02/2023 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 4 - 08/02/2023 - 09/02/2023 - 09:00 - 17:00
- Zynq UltraScale+ MPSoC for the Hardware Designer - 08/02/2023 - 09/02/2023 - 09:00 - 17:00
- Migrating to the Vitis Embedded Software Development IDE Workshop - 10/02/2023 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 13/02/2023 - 14/02/2023 - 09:00 - 17:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 13/02/2023 - 14/02/2023 - 09:00 - 17:00
- Design Closure Techniques ✅ - 16/02/2023 - 17/02/2023 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 16/02/2023 - 17/02/2023 - 09:00 - 17:00
- High-Level Synthesis with the Vitis HLS Tool - 20/02/2023 - 21/02/2023 - 09:00 - 17:00
- Workshop: Spartan-6 Migration to 7 series or UltraScale+ (PST timezone) ✅ - 23/02/2023 - 24/02/2023 - 08:30 - 12:00
- Workshop: Spartan-6 Migration to 7 series or UltraScale+ (CET timezone) ✅ - 23/02/2023 - 24/02/2023 - 09:30 - 13:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 07/03/2023 - 08/03/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 09/03/2023 - 10/03/2023 - 09:00 - 17:00
- DSP Design Using System Generator - 16/03/2023 - 17/03/2023 - 09:00 - 17:00
- Vitis Model Composer: A MATLAB and Simulink-based Product - 16/03/2023 - 17/03/2023 - 09:00 - 17:00
- Design Closure Techniques - 20/03/2023 - 21/03/2023 - 09:00 - 17:00
- Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite - 20/03/2023 - 21/03/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 27/03/2023 - 29/03/2023 - 09:00 - 17:00