Aankomende Evenementen
- Essential DSP Implementation Techniques for Xilinx FPGAs - 22/04/2024 - 23/04/2024 - 09:00 - 17:00
- Vitis Model Composer: A MATLAB and Simulink-based Product - 24/04/2024 - 25/04/2024 - 09:00 - 17:00
- High-Level Synthesis with the Vitis Unified IDE - 06/05/2024 - 07/05/2024 - 09:00 - 17:00
- Adaptive SoCs for System Architects - 13/05/2024 - 14/05/2024 - 09:00 - 17:00
- Embedded Systems Design - 13/05/2024 - 14/05/2024 - 09:00 - 17:00
- Embedded Systems Software Design - 15/05/2024 - 17/05/2024 - 09:00 - 17:00
- Operating Systems and Hypervisors in Adaptive SoCs - 15/05/2024 - 17/05/2024 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit & System-on-Module - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Design Closure Techniques - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing for Performance - 23/01/2050 - 10:00 - 18:00
- Advanced FPGA Implementation - 23/01/2050 - 11:00 - 19:00
- Xilinx Partial Reconfiguration Tools & Techniques - 01/01/2050 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00