Aankomende Evenementen
- Essential DSP Implementation Techniques for Xilinx FPGAs - 07/01/2050 - 09:00 - 17:00
- DSP Design Using System Generator - 07/01/2050 - 10:00 - 18:00
- High-Level Synthesis with the Vitis HLS Tool - 07/01/2050 - 11:00 - 19:00
- Embedded Systems Design - 09/01/2050 - 09:00 - 17:00
- Embedded Systems Software Design - 09/01/2050 - 10:00 - 18:00
- Zynq All Programmable SoC System Architecture - 10/01/2050 - 09:00 - 17:00
- Zynq UltraScale+ MPSoC for the System Architect - 10/01/2050 - 10:00 - 18:00
- Zynq UltraScale+ MPSoC for the Hardware Designer - 10/01/2050 - 11:00 - 19:00
- Migrating to the Vitis Embedded Software Development IDE Workshop - 11/01/2050 - 11:00 - 19:00
- Accelerating Applications with the Vitis Unified Software Environment - 11/01/2050 - 12:00 - 20:00
- Designing with Versal AI Engine 1: Architecture and Design Flow - 12/01/2050 - 09:00 - 17:00
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels - 12/01/2050 - 10:00 - 18:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/01/2050 - 12:00 - 20:00
- Designing with the Versal ACAP: Network on Chip - 12/01/2050 - 13:00 - 21:00
- Developing AI Inference Solutions with the Vitis AI Platform - 13/01/2050 - 09:00 - 17:00
- Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit & System-on-Module - 13/01/2050 - 09:00 - 17:00
- Designing with Multi-Gigabit Serial I/O - 14/01/2050 - 09:00 - 17:00
- Designing with Xilinx Serial Transceivers - 14/01/2050 - 10:00 - 18:00
- Designing with the Spartan-6 FPGA Families - 25/01/2050 - 11:00 - 19:00