Core|Vision offers FPGA training, as indicated in the training schedule below. Is your desired training not listed or does the date not fit in your agenda? Please contact Core|Vision to discuss how we can tailor this to your needs.
✅ indicates CONFIRMED TO RUN
May - 2024
| Date | Category | Training | Location | Price |
|---|---|---|---|---|
|
06 - 07
|
ACAP | High-Level Synthesis with the Vitis Unified IDE | Heesch |
-
|
|
13 - 14
|
Embedded | Adaptive SoCs for System Architects | Heesch |
-
|
|
13 - 14
|
Embedded | Embedded Systems Design | Heesch |
-
|
|
15 - 17
|
Embedded | Embedded Systems Software Design | Heesch |
-
|
|
15 - 17
|
Embedded | Operating Systems and Hypervisors in Adaptive SoCs | Heesch |
-
|
|
21 - 22
|
AI | Developing AI Inference Solutions with the Vitis AI Platform | Heesch |
€ 2.000,00
|
|
21 - 22
|
AI | Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit & System-on-Module | Heesch |
€ 2.000,00
|
|
21
|
vSync Circuits | Glitch Free clock gating and switching ✅ | Webinar |
€ 0,00
|
|
23 - 24
|
Workshop | Using AMD High Level Synthesis to supercharge your design performance Online Workshop ✅ | Free Workshop | |
|
29
|
vSync Circuits | Focusing on reset coding static analysis ✅ | Webinar |
€ 0,00
|
June - 2024
| Date | Category | Training | Location | Price |
|---|---|---|---|---|
|
12 - 13
|
FPGA | Design Closure Techniques | Heesch |
€ 2.000,00
|
|
12 - 13
|
FPGA | Designing with the IP Integrator Tool | Heesch |
€ 2.000,00
|
|
12 - 13
|
Connectivity | Designing with Xilinx Serial Transceivers | Heesch |
€ 2.000,00
|
July - 2024
| Date | Category | Training | Location | Price |
|---|---|---|---|---|
|
03 - 05
|
ACAP | Accelerating Applications with the Vitis Unified Software Environment | Heesch |
€ 3.000,00
|
|
03 - 04
|
ACAP | Designing with the Versal Adaptive SoC: Architecture | Heesch |
€ 2.000,00
|
|
05
|
ACAP | Designing with the Versal ACAP: Network on Chip | Heesch |
€ 1.000,00
|
|
08 - 09
|
FPGA | Designing FPGAs Using the Vivado Design Suite 1 | Heesch |
€ 2.000,00
|
|
08 - 09
|
FPGA | Designing FPGAs Using the Vivado Design Suite 3 | Heesch |
€ 2.000,00
|
|
10 - 11
|
FPGA | Designing FPGAs Using the Vivado Design Suite 2 | Heesch |
€ 2.000,00
|
|
10 - 11
|
FPGA | Designing FPGAs Using the Vivado Design Suite 4 | Heesch |
€ 2.000,00
|
|
31
|
Embedded | Migrating to the Vitis Embedded Software Development IDE | Heesch |
€ 1.000,00
|
August - 2024
| Date | Category | Training | Location | Price |
|---|---|---|---|---|
|
01 - 02
|
Digital Design | Essential Digital Design Techniques | Heesch |
€ 2.100,00
|
|
05 - 09
|
Doulos | Expert VHDL | Heesch |
€ 4.350,00
|
|
05 - 06
|
Doulos | Expert VHDL Design | Heesch |
€ 2.250,00
|
|
07 - 09
|
Doulos | Expert VHDL Verification | Heesch |
€ 3.125,00
|
|
14 - 15
|
Embedded | Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite | Heesch |
€ 2.000,00
|
|
14 - 15
|
FPGA | Designing with the UltraScale and UltraScale+ Architectures | Heesch |
€ 2.000,00
|
|
14 - 15
|
DSP | Essential DSP Implementation Techniques for Xilinx FPGAs | Heesch |
€ 2.000,00
|
|
14 - 15
|
FPGA | UltraFast Design Methodology | Heesch |
€ 2.000,00
|
|
26 - 30
|
Doulos | Comprehensive VHDL | Heesch |
€ 4.225,00
|
|
26 - 28
|
Doulos | VHDL for Designers | Heesch |
€ 3.075,00
|
|
29 - 30
|
Doulos | Advanced VHDL | Heesch |
€ 2.100,00
|
September - 2024
| Date | Category | Training | Location | Price |
|---|---|---|---|---|
|
03 - 04
|
ACAP | High-Level Synthesis with the Vitis Unified IDE | Heesch |
€ 2.000,00
|
|
05 - 06
|
DSP | Vitis Model Composer: A MATLAB and Simulink-based Product | Heesch |
€ 2.000,00
|
|
09 - 10
|
Embedded | Adaptive SoCs for System Architects | Heesch |
€ 2.000,00
|
|
09 - 10
|
Embedded | Embedded Systems Design | Heesch |
€ 2.000,00
|
|
09 - 10
|
Embedded | Zynq UltraScale+ MPSoC for the Hardware Designer | Heesch |
€ 2.000,00
|
|
11 - 13
|
Embedded | Embedded Systems Software Design | Heesch |
€ 3.000,00
|
|
11 - 13
|
Embedded | Operating Systems and Hypervisors in Adaptive SoCs | Heesch |
€ 3.000,00
|
|
11 - 12
|
Embedded | Zynq UltraScale+ MPSoC: Boot and Platform Management | Heesch |
€ 2.000,00
|
|
17 - 18
|
ACAP | Designing with Versal AI Engine: Architecture and Design Flow (1) | Heesch |
€ 2.000,00
|
|
19 - 20
|
ACAP | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) | Heesch |
€ 2.000,00
|