Designing with the Spartan-6 and Virtex-6 FPGA Families

Course Description

Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.

Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.

Note: A two-day Spartan-6 family only course or two-day Virtex-6 family only course is also available.

Release Dateimagescatsf01z

March 2011



Training Duration

3 days

Who Should Attend?

For those who have taken the Essentials of FPGA Design course


Software Tools

  • Xilinx ISE® Design Suite: Logic or System Edition 13.1


* This course focuses on the Spartan-6 and Virtex-6 architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 and Virtex-6 FPGAs
  • Specify the CLB resources and the available slice configurations for the Spartan-6 and Virtex-6 FPGAs
  • Define the block RAM and DSP resources available for Spartan-6 and Virtex-6 FPGAs
  • Properly design for the I/O block and SERDES resources
  • Identify the DCM, PLL, and clock routing resources included with each of these families
  • Identify the supported memory controllers for the Spartan-6 and Virtex-6 FPGAs
  • Properly code your HDL to get the most out of these devices
  • Describe the additional dedicated hardware for all the Spartan-6 and Virtex-6 families
  • Identify the features of the 7 series families

Full Course Outline

Day 1

  • Spartan-6 FPGA Overview
  • Virtex-6 FPGA Overview
  • CLB Architecture
  • HDL Coding Techniques
  • Lab 1: CLB Resources
  • Memory Resources
  • DSP Resources

Day 2

  • Lab 2: DSP Resources
  • Basic I/O Resources
  • Spartan-6 FPGA I/O Resources
  • Virtex-6 FPGA I/O Resources
  • Lab 3: I/O Resources
  • Basic Clocking Resources

Day 3

  • Spartan-6 FPGA Clocking Resources
  • Virtex-6 FPGA Clocking Resources
  • Lab 4: Clocking Resources
  • Memory Controllers
  • Dedicated Hardware

Lab Descriptions

  • Lab 1: CLB Resources – Using XST, synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Lab 2: DSP Resources – Using XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Lab 3: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.
  • Lab 4: Clocking Resources – Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.

AMD On Request

On Request

Cereslaan 24
5384 VT

€ 3.750,00
60 Xilinx Training Credits

Training brochure

Registration form


S6V6-21000 Designing with the Spartan-6 and Virtex-6 Families

€ 3.750,00


Booking Summary

x Standaardticket
€ 3.750,00
Total Price
€ 3.750,00