Glitch Free clock gating and switching
✅ indicates CONFIRMED TO RUN
- Date: Tuesday May 21, 2024
- Duration: 30 min (with live Q&A)
- Time: 11:00 – 11:30 (CET)
- Presenter: Dr Reuven Dobkin
- Attendance: FREE!
Webinar Overview
Safe clock gating and switching are required for low power and power-aware applications. Gating the clock reduces the dynamic power of the design, and clock-switching is required when a design shall support multiple operation clocking modes, e.g. for auto-negotiation. The clock gating and switching operations require special circuitry to eliminate clock glitches, that are deadly for synchronous designs. During this webinar, we will review such circuits, discussing both ASIC and FPGA implementations.
If you have any queries, please contact info@vsyncc.com
Date
21 May 2024
Location
Webinar
Online
Webinar
Price
€ 0,00
Information
Training brochure