Vivado Design Suite for ISE Software Project Navigator Users

Course Description

This course offers introductory training on the Vivado® Design Suite. This course is for experienced ISE® software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

vivado-flowLevel

FPGA 2

Course Duration

2 days

Audience

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

  • Digital design knowlegde
  • Basic knowledge of  VHDL or Verilog language

Recommended Recorded Videos

Software Tools

  • Vivado System Edition 2018.1

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

Day 1

  • UltraFast Design Methodology: Planning {Lecture, Demo}
  • UltraFast Design Methodology: Design Creation and Analysis {Lecture}
  • HDL Coding Techniques {Lecture}
  • Resets {Lecture, Lab}
  • Register Duplication {Lecture}
  • Synchronous Design Techniques {Lecture}
  • Introduction to the Vivado Design Suite {Lecture}
  • Introduction to Vivado Design Flows {Lecture}
  • Vivado Design Suite Project Mode {Lectures, Lab}
  • Synthesis and Implementation {Lecture, Lab}
  • Basic Design Analysis in the Vivado IDE {Lab, Demo}
  • Vivado Design Suite I/O Pin Planning {Lecture, Lab}

Day 2

  • Vivado IP Flow {Lecture, Lab, Demo}
  • Designing with IP Integrator {Lecture, Lab, Demo, Case Study}
  • Vivado Design Suite Non-Project Mode {Lecture}
  • Introduction to the Tcl Environment {Lecture, Lab}
  • Design Analysis Using Tcl Commands {Lecture, Lab, Demo}
  • Scripting in Vivado Design Suite Project Mode {Lecture, Lab}
  • Scripting in Vivado Design Suite Non-Project Mode {Lecture, Lab}

Topic Descriptions

Day 1

  • UltraFast Design Methodology: Planning – Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist.
  • UltraFast Design Methodology: Design Creation and Analysis – Overview of the methodology guidelines on design creation and analysis.
  • HDL Coding Techniques – Covers basic digital coding guidelines used in an FPGA design.
  • Resets – Investigates the impact of using asynchronous resets in a design. { + Lab}
  • Register Duplication – Use register duplication to reduce high fanout nets in a design.
  • Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.
  • Introduction to the Vivado Design Suite – Introduces the Vivado Design Suite.
  • Introduction to Vivado Design Flows – Introduces the Vivado design flows: the project flow and non-project batch flow.
  • Vivado Design Suite Project Mode – Create a project, add files to the project, explore the Vivado IDE, and simulate the design.{ + Lab}
  • Synthesis and Implementation – Create timing constraints according to the design scenario and synthesize and implement the design.
  • Basic Design Analysis in the Vivado IDE – Use the various design analysis features in the Vivado Design Suite.
  • Vivado Design Suite I/O Pin Planning – Use the I/UltraFast Design Methodology: Planning

Day 2

  • Vivado IP Flow – Customize IP, instantiate IP, and verify the hierarchy of your design IP.
  • Designing with IP Integrator – Use the Vivado IP integrator to create the uart_led subsystem.
  • Vivado Design Suite Non-Project Mode – Create a design in the Vivado Design Suite non-project mode.
  • Introduction to the Tcl Environment – Introduces Tcl (tool command language).
  • Design Analysis Using Tcl Commands – Analyze a design using Tcl commands.
  • Scripting in Vivado Design Suite Project Mode – Explains how to write Tcl commands in the project-based flow for a design.
  • Scripting in Vivado Design Suite Non-Project Mode – Write Tcl commands in the non-project batch flow for a design.


Datum
07 januari 2019 - 08 januari 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

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