Embedded Systems Design

Course Description

This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado Design Suite. The features and capabilities of both the Zynq All Programmable System on a Chip (SoC) and the MicroBlaze™ soft processor are covered in lectures and labs, in addition to general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.

The Xilinx Zynq All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

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Level

Embedded Hardware 3

Course Duration

2 days

Audience

Engineers who are interested in developing embedded systems with the Xilinx Zynq® All Programmable SoC or MicroBlaze soft processor core using the Embedded Development Kit.

Prerequisites

  • FPGA design experience
  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado® software implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

  • Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard or Kintex®-7 FPGA KC705 board*

* This course focuses on the Zynq-7000 All Programmable SoC and 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing a MicroBlaze™ or Cortex™-A9 processor using the Vivado IP integrator and Customization Wizard
  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
  • Create and integrate an IP-based processing system component in the Vivado Design Suite
  • Design and add a custom AXI interface-based peripheral to the embedded processing system
  • Simulate a custom AXI interface-based peripheral using a bus functional model (BFM)

Course Outline

Day 1

  • Embedded UltraFast Design Methodology
  • Overview of Embedded Hardware Development
  • Driving the IP Integrator Tool (Lab)
  • Overview of Embedded Software Development
  • Driving the SDK Tool (Lab)
  • AXI: Introduction
  • AXI: Variations
  • AXI: Transactions (Lab)
  • Introduction to Interrupts
  • Interrupts: Hardware Architecture and Support

Day 2

  • AXI: Connecting AXI IP
  • Using the Create and Import Wizard to Create a New AXI IP (Lab)
  • AXI: BFM Simulation (Lab)
  • MicroBlaze Processor Architecture Overview (Lab)
  • MicroBlaze Processor Block Memory Usage
  • Zynq-7000 All Programmable SoC Architecture Overview (Lab)

Topic Descriptions

Day 1

  • Embedded UltraFast Design Methodology – Outlines the different elements that comprise the Embedded Design Methodology.
  • Overview of Embedded Hardware Development – Overview of the embedded hardware development flow.
  • Driving the IP Integrator Tool – Describes how to access and effectively use the IPI tool.
  • Overview of Embedded Software Development – Reviews the process of building a user application.
  •  Driving the SDK Tool – Introduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application.
  • AXI: Introduction – Introduces the AXI protocol.
  • AXI: Variations – Describes the differences and similarities among the three primary AXI variations.
  • AXI: Transactions – Describes different types of AXI transactions.
  • Introduction to Interrupts – Introduces the concept of interrupts, basic terminology, and generic implementation.
  • Interrupts: Hardware Architecture and Support – Reviews the hardware that is typically available to help implement and manage interrupts.

Day 2

  • AXI: Connecting AXI IP – Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
  • Using the Create and Import Wizard to Create a New AXI IP – Explains how to use the Create and Import Wizard to create andpackage an AXI IP.
  • AXI: BFM Simulation Using Verification IP – Describes how to perform BFM simulation using the Verification IP.
  • MicroBlaze Processor Architecture Overview – Overview of the MicroBlaze microprocessor architecture.
  • MicroBlaze Processor Block Memory Usage – Highlights how block RAM can be used with the MicroBlaze processor.
  • Zynq-7000 All Programmable SoC Architecture Overview – Overview of the Zynq-7000 All Programmable SoC architecture.
  • Zynq UltraScale+ MPSoC Architecture Overview – Overview of the Zynq UltraScale+ MPSoC architecture.

Embedded


Datum
18 februari 2019 - 19 februari 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

EMBD HW

€ 1.500,00