Designing with Xilinx Serial Transceivers

Course Description

Learn how to employ serial transceivers in 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC designs.
The focus is on:
  • Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
  • Utilizing the Transceivers Wizards to instantiate transceiver primitives
  • Synthesizing and implementing transceiver designs
  • Taking into account board design as it relates to the transceivers
  • Testing and debugging

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Level

Connectivity 3

Training Duration

2 days

Audience

FPGA designers and logic designers

Prerequisites

  • Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
  • Familiarity with logic design (state machines and synchronous design)
  • Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

  • Vivado® System Edition 2016.3
  • Mentor Graphics QuestaSim simulator 10.4

Hardware

  • Architecture: 7 series and UltraScale FPGAs
  • Demo board: Kintex-7 FPGA KC705 board

 

Skills Gained

This course focuses on the UltraScaleand 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.After completing this comprehensive training, you will have the necessary skills to:

  • Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs
  • Effectively utilize the following features of the gigabit transceivers:
    • 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
    • Pre-emphasis and linear equalization
  • Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
  • Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
  • Use the IBERT design to verify transceiver links on real hardware

Course Outline

Day 1

  • 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
  • 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
  • Transceiver IP Generation –Transceiver Wizard
  • Lab 1: Transceiver Core Generation
  • Transceiver Simulation
  • Lab 2: Transceiver Simulation
  • PCS Layer General Functionality
  • PCS Layer Encoding
  • Lab 3: 64B/66B Encoding

Day 2

  • Transceiver Implementation
  • Lab 4: Transceiver Implementation
  • PMA Layer Details
  • PMA Layer Optimization
  • Lab 5: IBERT Design
  • Transceiver Test and Debugging
  • Lab 6: Transceiver Debugging
  • Transceiver Board Design Considerations
  • Transceiver Application Example

Lab Descriptions

  • Lab 1:Transceiver Core Generation –Use the Transceivers Wizard to create instantiation templates.
  • Lab 2: Transceiver Simulation –Simulate the transceiver IP by using the IP example design.
  • Lab 3: 64B/66B Encoding –Generate a 64B/66Btransceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
  • Lab 4: Transceiver Implementation –Implement the transceiver IP by using the IP example design.
  • Lab 5: IBERT Design –Verify transceiver links on real hardware.
  • Lab 6: Transceiver Debugging –Debug transceiver links.

Connectivity


Datum
15 april 2019 - 16 april 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

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