Designing FPGAs Using the Vivado Design Suite 3

Course Description

This course demonstrates timing closure techniques, such as baselining,.pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

PrintLevel

FPGA 3

Course Duration

2 days

Audience

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite.

Prerequisites

Optional  Videos

Software Tools

  • Vivado System Edition 2018.1

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems. and requires less design debugging later in the development cycle
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Identify timing closure techniques using the Vivado Design Suite

Course Outline

Day 1

  • UltraFast Design Methodology Introduction 3 {Lecture}
  • Timing Simulation {Lecture, Lab}
  • Vivado Design Suite Non-Project Based Batch Flow {Lecture, Lab}
  • Revision Control Systems in the Vivado Design Suite {Lecture, Lab}
  • Baselining {Lecture, Lab, Demo}
  • Pipelining {Lecture, Lab}
  • Inference {Lecture, Lab}
  • Design Conversion {Lecture, Lab}

Day 2

  • Synchronization Circuits {Lecture, Demo}
  • Report Data Sheet {Lecture, Demo}
  • Report Clock Interaction {Lecture, Demo}
  • Configuration Modes {Lecture}
  • Configuration Modes {Lecture}
  • Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}
  • Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}
  • JTAG-to-AXI-Master Core {Lecture, Demo}
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}
  • Manipulate Design Properties Using Tcl {Lecture, Lab}

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction 3 – Introduces the methodology guidelines covered in this course.
  • Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware.
  • Vivado Design Suite Non-Project Based Batch Flow – Create a design in the Vivado Design Suite non-project batch flow.
  • Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.
  • Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  • Pipelining – Use pipelining to improve design performance.
  • Inference – Infer xilinx dedicated hardware resources by writing appropriate HDL code.
  • Design Conversion – Learn how a generic processor design was optimized for the 7 series device architecture. with basic design changes that impacted the dedicated hardware usage, design speed, and device utilization.

Day 2

  • Synchronization Circuits – Use synchronization circuits for clock domain crossings.
  • Report Data Sheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  • Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.
  • Configuration Modes – Understand various configuration modes and select the suitable mode for a design.
  • Dynamic Power Estimation Using Vivado Report Power.– Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
  • Remote Debugging Using the Vivado Logic Analyzer.– Use the Vivado logic analyzer to configure an FPGA, set up triggering,.and view the sampled data from a remote location.
  • JTAG-to-AXI-Master Core. – Use this debug core to write/read data to/from a peripheral connected to an AXI interface.
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer .– Use TSM code to trigger the ILA and capture data in the Vivado logic analyzer.
  • Manipulate Design Properties Using Tcl – Query your design and make pin assignments using various Tcl commands.


Datum
18 maart 2019 - 19 maart 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

FPGA VDES3

€ 1.500,00