Defining Timing Constraints using SDC
✅ indicates CONFIRMED TO RUN
- Date: Friday May 13, 2022
- Duration: 1 hour (with live Q&A)
- Time: 11:00 – 12:00
- Cost: Free!
Overview
This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.
As well as getting an overview of what SDC is and the basic terminology, you will learn how to define clocks, how to set up timing for the I/Os and how to define exceptions like false-paths and multicycle-paths; everything you need to set up timing in a simple design.
Content Summary:
– What is SDC, and why is it important?
– SDC Basics
– Defining Clocks
– Defining Interface Timing
– Defining Exceptions
The webinar will also feature a working SDC example design by Microchip® applied to a PolarFire® FPGA using the Libero® SoC Design Suite.
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Datum
13 mei 2022
Locatie
Webinar
Online
Webinar
Prijs
€ 0,00
Informatie
Training brochure