Request for online training
Aankomende Evenementen
- Comprehensive VHDL - 29/04/2024 - 03/05/2024 - 09:00 - 17:00
- VHDL for Designers - 29/04/2024 - 01/05/2024 - 09:00 - 17:00
- Advanced VHDL - 02/05/2024 - 03/05/2024 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Essential Digital Design Techniques - 04/07/2024 - 05/07/2024 - 09:00 - 17:00
- Xilinx Partial Reconfiguration Tools & Techniques - 01/01/2050 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 4 - 02/01/2050 - 12:00 - 20:00
- Vivado Design Suite for ISE Software Project Navigator Users - 03/01/2050 - 09:00 - 17:00
- Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users - 03/01/2050 - 10:00 - 18:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 07/01/2050 - 09:00 - 17:00
- DSP Design Using System Generator - 07/01/2050 - 10:00 - 18:00
- High-Level Synthesis with the Vitis HLS Tool - 07/01/2050 - 11:00 - 19:00
- Embedded Systems Design - 09/01/2050 - 09:00 - 17:00
- Embedded Systems Software Design - 09/01/2050 - 10:00 - 18:00