Request for online courses
Aankomende Evenementen
- Designing with the Versal ACAP: Network on Chip - 03/02/2023 - 09:00 - 17:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 13/02/2023 - 14/02/2023 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 16/02/2023 - 17/02/2023 - 09:00 - 17:00
- Workshop: Spartan-6 Migration to 7 series or UltraScale+ (PST timezone) ✅ - 23/02/2023 - 24/02/2023 - 08:30 - 12:00
- Workshop: Spartan-6 Migration to 7 series or UltraScale+ (CET timezone) ✅ - 23/02/2023 - 24/02/2023 - 09:30 - 13:00
- Essential Digital Design Techniques - 13/03/2023 - 14/03/2023 - 09:00 - 17:00
- Comprehensive VHDL - 17/04/2023 - 21/04/2023 - 09:00 - 17:00
- VHDL for Designers - 17/04/2023 - 19/04/2023 - 09:00 - 17:00
- Advanced VHDL - 20/04/2023 - 21/04/2023 - 09:00 - 17:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 25/04/2023 - 26/04/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 15/06/2023 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 4 - 02/01/2050 - 12:00 - 20:00
- Vivado Design Suite for ISE Software Project Navigator Users - 03/01/2050 - 09:00 - 17:00
- Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users - 03/01/2050 - 10:00 - 18:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00