Aankomende Evenementen
- Vivado Design Suite for ISE Software Project Navigator Users - 03/01/2050 - 09:00 - 17:00
- Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users - 03/01/2050 - 10:00 - 18:00
- Essential Design with the PlanAhead Analysis and Design Tool - 24/01/2050 - 09:00 - 17:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00
- Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite - 05/01/2050 - 10:00 - 18:00
- Essential DSP Implementation Techniques for Xilinx FPGAs - 07/01/2050 - 09:00 - 17:00
- DSP Design Using System Generator - 07/01/2050 - 10:00 - 18:00
- High-Level Synthesis with the Vitis HLS Tool - 07/01/2050 - 11:00 - 19:00
- Embedded Systems Design - 09/01/2050 - 09:00 - 17:00
- Embedded Systems Software Design - 09/01/2050 - 10:00 - 18:00
- Zynq All Programmable SoC System Architecture - 10/01/2050 - 09:00 - 17:00
- Zynq UltraScale+ MPSoC for the System Architect - 10/01/2050 - 10:00 - 18:00
- Zynq UltraScale+ MPSoC for the Hardware Designer - 10/01/2050 - 11:00 - 19:00
- SDSoC Development Environment and Methodology - 11/01/2050 - 09:00 - 17:00
- Migrating to the Vitis Embedded Software Development IDE Workshop - 11/01/2050 - 11:00 - 19:00
- Accelerating Applications with the Vitis Unified Software Environment - 11/01/2050 - 12:00 - 20:00
- Designing with Versal AI Engine 1: Architecture and Design Flow - 12/01/2050 - 09:00 - 17:00
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels - 12/01/2050 - 10:00 - 18:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/01/2050 - 12:00 - 20:00
- Designing with the Versal ACAP: Network on Chip - 12/01/2050 - 13:00 - 21:00