- Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
- Engineers who are about to embark on the first VHDL design project
- Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
What will you learn?
- The VHDL language concepts constructs essential for complex FPGA and ASIC design
- The VHDL language constructs and coding styles that enable sophisticated test benches
- How to code hierarchical designs using multiple VHDL design libraries
- How to write re-usable, parameterisable VHDL code by exploiting generics and data types
- How to run gate-level simulations
23 juli 2020 - 24 juli 2020
Online or Heesch
29 Xilinx Training Credits
Registratie op aanvraag, neem contact op met ons.