Bug discovery by static analysis in VHDL

 

indicates CONFIRMED TO RUN

  • Date: Tuesday June 15, 2021
  • Duration: 25 min (with live Q&A)
  • Time: 11:00 – 11:25 (CET)
  • Presenter: Dr Reuven Dobkin
  • Attendance: FREE!

 

Webinar Overview

During this short webinar, we will exemplify a few buggy RTL patterns that can be discovered by an automatic static analysis, leading to prompt bug-fix instead of a much longer verification by simulation / formal analyses.

Patterns to be discussed:

  1. Signal contention
  2. Latches
  3. FSM issues: unreachable, trap states
  4. Tri-state buffers issues

If you have any queries, please contact info@vsyncc.com

vSync Circuits


Date
15 June 2021

Location
Webinar
Online

Webinar

Price
€ 0,00

Information
Training brochure

Registration form

Registration on demand, please contact us.