VHDL for Designers
Course Description
Audience
- Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
- Engineers who are about to embark on the first VHDL design project
- Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
What will you learn?
- The VHDL language concepts and constructs essential for FPGA design
- How to write VHDL for effective RTL synthesis
- How to target VHDL code to an FPGA device architecture
- How to write simple VHDL test benches
- The tool flow from VHDL through simulation, synthesis and place-and-route
- How to write high quality VHDL code that reflects best practice in the industry
Pre-requisites
Delegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design. No previous knowledge of VHDL or a software language is required.
Delegates attending only the Advanced VHDL module must have some hardware design experience, and have completed the VHDL for Designers module or an equivalent course. We have found that delegates frequently overestimate their own capabilities. If in doubt, you will probably benefit from attending the full Comprehensive VHDL course.
Course materials
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos Golden Reference Guide for VHDL language, syntax, semantics and tips
- Tool tour guides (to support the tools and technologies of your choice)
- Design flow guide for ASIC and the leading FPGA/CPLD technologies