Expert VHDL Verification

Course Descriptionexpvhdl_learningpath

Expert VHDL Verification is a 3 days course as part of the intensive 5-day Expert VHDL class.

  • Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification.

The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.

Who should attend?

  • Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
  • Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems

What will you learn?

  • A set of VHDL language features that go beyond what is taught on a basic training class
  • A deeper understanding of the VHDL language and how to apply it, enabling you to troubleshoot VHDL simulation and synthesis problems with ease
  • The principles and details of how to approach the problem of design verification using VHDL
  • How to structure and write large and complex VHDL test benches
  • The principles and details of how to write behavioural models of hardware components in VHDL
  • To produce smaller and faster hardware design using VHDL and RTL synthesis tools
  • A solid introduction to the topic of behavioural synthesis from VHDL, enabling you to judge the applicability and effectiveness of behavioural synthesis in your design context
  • The details of a VHDL coding style to facilitate code re-use and how to package IP for re-use
  • An introduction to IEEE 1076-2007c (VHPI) and the proposed VHDL 2008


This is an advanced language and methodology training class. Prior attendance of the Doulos Comprehensive VHDL class (or equivalent) is required, and at least 6 months of ‘live’ project experience using VHDL is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis using VHDL.


22 maart 2017 - 24 maart 2017

Cereslaan 24
5384 VT

€ 0,00
40 Xilinx Training Credits

Training brochure


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