Efficient Handling of Clocked Logic

✅ indicates CONFIRMED TO RUN

• Date: Wednesday November 23, 2022
• Duration: 30min (with live Q&A)
• Time: 11:00 – 11:30(CET)
  
• Presenter: Dr Reuven Dobkin
  
• Attendance: FREE!

Webinar Overview

During this short webinar we will review rules for correct and efficient coding of clocked RTL design parts. A few common coding patterns and coding mistakes for synchronous process/always statements will be discussed. We will show how these issues can be automatically identified and reported.

If you have any queries, please contact info@vsyncc.com