Design Closure Techniques


Course Description

Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster timetomarket results.

The emphasis of this course is on:

  • Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
  • Using recommended coding techniques
  • Creating a test bench and running simulation for functional verification
  • Applying initial design checks and reviewing timing summary and methodology reports for a design
  • Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
  • Performing quality of results (QoR) assessments at different stages to improve the QoR score
  • Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
  • Reviewing the importance of power closure and device selection
  • Estimating power consumption by using the Vivado® Design Suite Power Report utility and performing power optimization on a design
  • Identifying Versal® ACAP power and thermal solutions
  • Utilizing architecture features to improve a design’s power consumption




Course Duration

2 days

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure


  • Basic knowledge of FPGA and SoC architecture and HDL coding techniques.
  • Basic knowledge of the Vivado® Design Suite

Software Tools

  • Vivado Design Suite 2022.1


  • Architecture: UltraScale™ FPGAs and Versal® ACAPs

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe what is design closure is as well as its three pillars
  • Create a test bench and run simulation for functional verification
  • Resolve setup and hold violations by reducing logic delay and net delay
  • Improve clock skew and clock uncertainty
  • Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
  • Perform QoR assessment at different stages and improve the QoR score
  • Implement Intelligent Design Runs (IDR)
  • Apply the power closure flow for better time to market
  • Estimate power consumption by using the Xilinx Power Estimator (XPE)
  • Describe Versal ACAP power and thermal solutions
  • Perform power optimization on a design

Course Outline

Day 1

  • Introduction to Design ClosureDefines what design closure is and identifies the three pillars of design closure. {Lecture}
  • HDL Coding Techniques – Covers basic digital coding guidelines used in an FPGA design. {Lecture}
  • Creating a Test Bench – Describes the design components of a test bench, the different test bench types and how a selfchecking test bench can be constructed. {Lecture}
  • Behavioral Simulation – Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}
  • Timing SimulationSimulate the design postimplementation to verify that a design works properly on hardware. {Lecture, Lab}
  • Introduction to Clocking and Static Timing Analysis (STA) – Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}
  • Introduction to UltraFast Design Methodology Timing Closure – Provides an overview of the various stages of the UltraFast Design Methodology for timing closure. {Lecture}
  • Baselining – Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab}
  • Setup and Hold Violation Analysis – Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}
  • Reducing Logic DelayDescribes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}
  • Reducing Net Delay – Reviews different techniques to reduce congestion and net delay. {Lecture, Lab}
  • Improving Clock Skew – Describes how to apply various techniques to improve clock skew. {Lecture}
  • Improving Clock Uncertainty – Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}

Day 2

  • Clock Domain Crossing (CDC) and Synchronization Circuits – Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab}
  • QoR Reports Overview – Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab}
  • Intelligent Design Runs (IDR) – Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}
  • Understanding Design Power for Better Time to Market – Outlines the types of design power, describes the power closure flow, and identifies methods for bringing down the power of a device. {Lecture, Lab}
  • Xilinx Power Estimator Spreadsheet – Demonstrates how to estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
  • Versal ACAP: Power and Thermal Solutions – Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered. {Lecture}
  • Design Power ConstraintsDescribes what design power constraints are and how to use the Power Constraints Advisor tool. Power rail constraints are also covered. {Lecture}
  • Power Management TechniquesIdentifies techniques used for low power design. {Lecture}
  • Power Analysis and Optimization Using the Vivado Design Suite – Covers how to use report power commands to estimate power consumption. {Lecture, Lab}



16 February 2023 - 17 February 2023

Cereslaan 24
5384 VT

€ 0,00
20 Xilinx Training Credits

Training brochure

Registration form

Registration on demand, please contact us.