Design Closure Techniques ✅

What's New for 2023.2

• New module: Versal Adaptive SoC: Timing Closure Techniques.
• All labs have been updated to the latest software versions.

Level

FPGA 2

Course Duration

2 days

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure.

Prerequisites

• Basic knowledge of FPGA and SoC architecture and HDL coding techniques.
• Basic knowledge of the Vivado® Design Suite.

Software Tools

• Vivado Design Suite 2023.2.

Hardware

• Architecture: UltraScale™ FPGAs and Versal adaptive SoCs.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe what is design closure is as well as its three pillars.
• Create a test bench and run simulation for functional verification.
• Resolve setup and hold violations by reducing logic delay and net delay.
• Improve clock skew and clock uncertainty.
• Identify clock domain crossings (CDC) and scenarios that require synchronization circuits.
• Perform QoR assessment at different stages and improve the QoR score.
• Implement Intelligent Design Runs (IDR).
• Apply the power closure flow for better time to market.
• Estimate power consumption by using the Xilinx Power Estimator (XPE).
• Describe Versal ACAP power and thermal solutions.
• Perform power optimization on a design.

Course Outline

Day 1

Introduction

• Introduction to Design Closure
  Defines what design closure is and identifies the three pillars of design closure. {Lecture}
  

Functional Closure

• HDL Coding Techniques
  Covers basic digital coding guidelines used in an FPGA design. {Lecture}
• Platform Creation for the Versal ACAP
  Reviews the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis™ environment. {Lecture}
• Behavioral Simulation
  Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}
• Creating a Test Bench
  Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed. {Lecture}
  

Timing Closure

• Static Timing Analysis (STA)
  Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}
• UltraFast Design Methodology Timing Closure
  Provides an overview of the various stages of the UltraFast Design Methodology for timing closure. {Lecture}
• Baselining
  Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab}
• Setup and Hold Violation Analysis
  Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}
• Reducing Logic Delay
  Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}
• Reducing Net Delay
  Reviews different techniques to reduce congestion and net delay. {Lecture, Lab}
• Improving Clock Skew
  Describes how to apply various techniques to improve clock skew. {Lecture}
• Improving Clock Uncertainty
  Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}
• QoR Reports Overview
  Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab}

Day 2

Timing Closure (continued)

• Clock Domain Crossing (CDC) and Synchronization Circuits
  Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab}
• Intelligent Design Runs (IDR)
  Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

Power Closure

• Understanding Design Power for Better Time to Market
  Outlines the types of design power, describes the power closure flow, and identifies methods for bringing down the power of a device. {Lecture, Lab}
• Xilinx Power Estimator Spreadsheet
  Demonstrates how to estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
• Versal ACAP: Power and Thermal Solutions
  Discusses the power domains in the Versal ACAP as well as power optimization and analysis techniques. Thermal design challenges are also covered. {Lecture}
• Design Power Constraints
  Describes what design power constraints are and how to use the Power Constraints Advisor tool. Power rail constraints are also covered. {Lecture}
  
• Power Management Techniques
  Identifies techniques used for low power design. {Lecture}
  
• Power Analysis and Optimization Using the Vivado Design Suite
  Covers how to use report power commands to estimate power consumption. {Lecture, Lab}