Zynq UltraScale+ MPSoC for the Hardware Designer

Zynq UltraScale+ MPSoC for the Hardware Designer

Course Description

This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.The emphasis is on:

• Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• Reviewing the various power domains and their control structure
• Illustrating the processing system (PS) and programmable logic (PL) connectivity
• Utilizing QEMU to emulate hardware behavior

Level

Embedded Hardware 3

Training Duration

2 days

Audience

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.e

Prerequisites

• Suggested: Understanding of the Zynq-7000 architecture
• Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools

• Vivado® Design Suite 2022.2
• Vitis unified software platform 2022.2
• Hardware emulation environment:
  • VirtualBox
  • QEMU
  • Ubuntu desktop
  • PetaLinux

Hardware

• Zynq UltraScale+ MPSoC ZCU104 board*

* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• List the various power domains and how they are controlled
• Describe the connectivity between the processing system (PS) and programmable logic (PL)
• Utilize QEMU to emulate hardware behavior

Course Outline

Day 1

• Application Processing Unit – Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster isconfigured and managed. {Lectures, Lab}
• HW-SW Virtualization – Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used. {Lectures, Demo, Lab}
• Real-Time Processing Unit – Focuses on the real-time processingmodule (RPU) in the PS, which is comprised of a pair of Cortex processors and supporting elements.. {Lectures, Demo, Lab}
• QEMU – Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available. {Lectures, Demos}
• Booting – How to implement the embedded system, including the boot process and boot image creation. {Lectures, Lab}
• First Stage Boot Loader – Demonstrates the process of developing, customizing, and debugging this mandatory piece of code. {Lecture, Demo}

Day 2

• Video – Introduction to video, video codecs, and the Video Codec Unit available in the Zynq UltraScale MPSoC. {Lectures}
• System Protection – Covers all the hardware elements that support the separation of software domains. {Lectures}
• Clocks and Resets – Overview of clocking and reset, focusing more on capabilities than specific implementations. {Lectures, Demos}
• AXI – Understanding how the PS and PL connect enables designers to create more efficient systems. {Lectures, Demo, Lab}
• Power Management – Overview of the PMU and the power-saving features of the device. {Lectures, Lab}
• Debugging Using Cross-Triggering – Illustrates how HW-SW cross-triggering techniques can uncover issues. {Lecture, Lab}