• Vivado® Design Suite 2021.2
• Vitis™ unified software platform 2021.2

• Architecture: Zynq-7000 All Programmable SoC*
• Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will know how to:

• Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
• Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC
• Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
• Analyze the tradeoffs and advantages of performing a function in software versus PL

Day 1

• Overview Provides a general overview of the Zynq SoC. {Demo}
  
• Application Processor Unit (APU) Explores the individual components that comprise the APU. {Lab}
  
• Neon Co–Processor Describes the Neon co–processor that is the companion to each Cortex–A9 processor.
  
• Input/Output Peripherals Introduces the components that comprise the IOP block of the Zynq device PS. {Demo}
  
• PS Peripherals
  ○ Low–Speed: Overview: Introduces the low–speed peripherals in the Zynq SoC. {Lab}
  ○ Low–Speed: UART: Introduces the UART low–speed peripheral. {Demo}
  ○ Low–Speed: CAN: Introduces the CAN low–speed peripheral. {Demo}
  ○ Low–Speed: I2C: Introduces the I2C low–speed peripheral.
  ○ Low–Speed: SD/SDIO: Introduces the SD/SDIO low–speed peripheral.
  ○ Low–Speed: SPI: Introduces the SPI low–speed peripheral.
  ○ Low–Speed: GPIO: Introduces the GPIO low–speed peripheral.
  ○ High–Speed: USB: Introduces the USB high–speed peripheral.
  ○ High–Speed: Gigabit Ethernet: Introduces the Gigabit Ethernet high–speed peripheral. {Lab}
  
• DMA Controller (DMAC)
  Explores the operation of the DMAC, which is located in the APU. {Lab}
  
• DMA
  ○ Introduction and Features: Introduces the direct memory access controller.
  ○ Block Design and Interrupts: Introduces the DMA block design and the DMA interrupts.
  ○ Read and Write: Introduces the concepts behind DMA reading and writing.

Day 2

• AXI
  ○ Introduction: Introduces the AXI protocol.
  ○ Variations: Describes the differences and similarities among the three primary AXI variations.
  ○ Transactions: Describes different types of AXI transactions. {Demo, Lab}
  
• PS–PL Interface
  Describes in detail the PS interconnect and how it affects PL architecture decisions. {Demo, Lab}
  
• Memory Resources
  Explains the operation of the on–chip (OCM) memory and various memory controllers located in the PS. {Demo}
  
• Booting Explains the boot process of the PC and configuration of the PL. {Lab}
  
• Meeting Performance Goals Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques. {Lab}
• Hardware Design Discusses the use and configuration of the PS in a hardware design.
  
• Software Design Explores the software side of the Zynq device. {Demo, Lab}
  
• Debugging Introduces debug tools and methodology on the Zynq SoC. {Lab}
  
• Tools and Reference Designs Describes Xilinx–provided reference design platforms, use cases, and third–party operating systems and tools for the Zynq SoC.