Zynq All Programmable SoC System Architecture

Course Description

Provides experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.
This course covers:

 
  • Identifying the features and benefits of the Zynq SoC architecture
  • Describing the architecture of the Arm® Cortex™A9 processorbased processing system (PS) and the connections to the programmable logic (PL)
  • Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupts, and memory controllers
  • Effectively accessing and using the PS DDR controller from PL user logic
  • Interfacing PLtoPS connections efficiently
  • Employing best practice design techniques for implementing functions in the PS or PL

    zynq-7000diagramLevel

Embedded Architect 3

Course Duration

2 days

Audience

  • System architects who are interested in architecting a system on a chip using the Zynq All Programmable SoC.

Prerequisites

  • Digital system architecture design experience
  • Basic understanding of microprocessor architecture
  • Basic understanding of C programming
  • Basic HDL modeling experience

Software Tools

  • Vivado® Design Suite 2021.2
  • Vitis™ unified software platform 2021.2

Hardware

  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)
  • Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC
  • Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals
  • Analyze the tradeoffs and advantages of performing a function in software versus PL

Day 1

  • Overview Provides a general overview of the Zynq SoC. {Demo}
  • Application Processor Unit (APU) Explores the individual components that comprise the APU. {Lab}
  • Neon CoProcessor Describes the Neon coprocessor that is the companion to each CortexA9 processor.
  • Input/Output Peripherals Introduces the components that comprise the IOP block of the Zynq device PS. {Demo}
  • PS Peripherals
    LowSpeed: Overview: Introduces the lowspeed peripherals in the Zynq SoC. {Lab}

    LowSpeed: UART: Introduces the UART lowspeed peripheral. {Demo}

    LowSpeed: CAN: Introduces the CAN lowspeed peripheral. {Demo}

    LowSpeed: I2C: Introduces the I2C lowspeed peripheral.

    LowSpeed: SD/SDIO: Introduces the SD/SDIO lowspeed peripheral.

    LowSpeed: SPI: Introduces the SPI lowspeed peripheral.

    LowSpeed: GPIO: Introduces the GPIO lowspeed peripheral.

    HighSpeed: USB: Introduces the USB highspeed peripheral.

    HighSpeed: Gigabit Ethernet: Introduces the Gigabit Ethernet highspeed peripheral. {Lab}

  • DMA Controller (DMAC)
    Explores the operation of the DMAC, which is located in the APU. {Lab}

  • DMA
    Introduction and Features: Introduces the direct memory access controller.

    Block Design and Interrupts: Introduces the DMA block design and the DMA interrupts.

    Read and Write: Introduces the concepts behind DMA reading and writing.

Day 2

  • AXI
    Introduction: Introduces the AXI protocol.

    Variations: Describes the differences and similarities among the three primary AXI variations.

    Transactions: Describes different types of AXI transactions. {Demo, Lab}

  • PSPL Interface
    Describes in detail the PS interconnect and how it affects PL architecture decisions. {Demo, Lab}

  • Memory Resources
    Explains the operation of the onchip (OCM) memory and various memory controllers located in the PS. {Demo}

  • Booting Explains the boot process of the PC and configuration of the PL. {Lab}
  • Meeting Performance Goals Focuses on Zynq device performance, including DDR access from the PL, DMA considerations, and power control and reduction techniques. {Lab}
  • Hardware Design Discusses the use and configuration of the PS in a hardware design.
  • Software Design Explores the software side of the Zynq device. {Demo, Lab}
  • Debugging Introduces debug tools and methodology on the Zynq SoC. {Lab}
  • Tools and Reference Designs Describes Xilinxprovided reference design platforms, use cases, and thirdparty operating systems and tools for the Zynq SoC.

Embedded


Datum
06 oktober 2022 - 07 oktober 2022

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 0,00
of
20 Xilinx Training Credits

Informatie
Training brochure