Xilinx Partial Reconfiguration Tools & Techniques

Course Description

This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design. You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow. This course also demonstrates how to use thee PR controller and PR decoupler IP in the PR process. You will also gain an understanding of PR implementation in an embedded system environment.

This course covers both the tool flow and mechanics of successfully creating a PR design. This course also covers both UltraScale™ and 7 series architecture design requirements, recommendations, and expectations for PR systems. In addition, it describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications. You will also identify techniques to debug PR designs.

fpga-pr

Level

FPGA 4

Training Duration

2 days

Audience

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques

Prerequisites

Software Tools

  • Vivado HLx 2018.1

Hardware

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

** The UltraScale architecture versions of the “Using the PRC IP in a Partial Reconfiguration Design” lab and the “Using ILA Cores to Debug Partial Reconfiguration Designs” lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The “Partial Reconfiguration in Embedded Systems” lab requires a ZedBoard for implementation.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Build and assemble a Partially Reconfigurable system (UltraScale, 7 series, and Zynq® devices)
  • Define PR regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a PR Design
  • use the ICAP and PCAP components to deliver the Partially Reconfigurable systems
  • Identify how Partial Reconfiguration affects various silicon resources, including block RAM, IOBs, fabric, clock buffers, and MGTs
  • Implement a Partial Reconfiguration system using the following techniques:
    • Direct JTAG connection
    • Floorplanning
    • Timing constraints and analysis
  • Implement a PR system using the PRC IP
  • Implement a PR system in an embedded environment
  • Debug PR designs

Course Outline

Day 1

  • Introduction toPartial Reconfiguration
  • Demo: Introduction to Partial Reconfiguration
  • Partial Reconfiguration Tool Flow
  • Lab 1: Partial Reconfiguration Flow
  • Lab 2: Partial Reconfiguration Project FLow
  • Lab 3: Floorplanning the PR Design
  • Optional: FPGA Configuration Overview
  • Partial Reconfiguration Bitstreams
  • Demo: Partial Reconfiguration Controller (PRC) IP
  • Partial Reconfiguration Design Recommendations
  • Lab 4: Using the Partial Reconfiguration Controller in a PR Design

Day 2

  • Partial Reconfiguation: Managing Timing
  • Lab 5: Partial Reconfiguration Timing Analysis and Constraints
  • Partial Reconfiguration in Embedded Systems
  • Lab 6: Partial Reconfiguration in Embedded Systems
  • Debugging Partial Reconfiguration Designs
  • Lab 7: Debugging a Partial Reconfiguration Design
  • Partial Reconfiguration Design Recommendations
  • PCIe Core and Partial Reconfiguration


Datum
11 februari 2019 - 12 februari 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

FPGA PR

€ 1.500,00