Webinar Overview:

Digital designers have been talking about design reuse for 30 years or so. Given that writing the testbench can be as much, if not more, effort than creating the design, testbench reuse is just as important, if not more. A structured testbench enables a powerful testbench to be designed that can much more easily be reused across block- and chip-level testing, across projects and across products.

This webinar introduces some modern verification concepts and shows how you can create a structured testbench in VHDL by presenting a VHDL testbench methodology.

Topics:

• Structured Testbench Overview
• Stimulus Generation and BFMs
• Checkers and Scoreboards
• Random Stimulus and Functional Coverage
• Other Testbench Features

Coding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on EDA Playground.

Attendance is free of charge