Writing Structured Testbenches in VHDL
✅ indicates CONFIRMED TO RUN
- Datum: woensdag 28 oktober, 2020
- Duur: 1 uur (met live Q&A)
- Tijd: 11:00 – 12:00
- Spreker: Brian Jensen
- Prijs: GRATIS!
Digital designers have been talking about design reuse for 30 years or so. Given that writing the testbench can be as much, if not more, effort than creating the design, testbench reuse is just as important, if not more. A structured testbench enables a powerful testbench to be designed that can much more easily be reused across block- and chip-level testing, across projects and across products.
This webinar introduces some modern verification concepts and shows how you can create a structured testbench in VHDL by presenting a VHDL testbench methodology.
- Structured Testbench Overview
- Stimulus Generation and BFMs
- Checkers and Scoreboards
- Random Stimulus and Functional Coverage
- Other Testbench Features
Brian Jensen , Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
Attendance is free of charge
28 oktober 2020