Workshop: Spartan-6 Migration to 7 series or UltraScale+
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In collaboration with Doulos & AMD Xilinx, Core|Vision organizes this free Workshop: Spartan-6 Migration to 7 series or UltraScale+. This free online workshop covers all the necessary steps to migrate a Spartan-6 design made in ISE to the 7-Series or UltraScale/Ultrascale+ devices using the Vivado ML tools.
The emphasis of this workshop is on:
- Compare Spartan-6 with Spartan-7 Architecture
- Migration flow
- Introduction to Vivado ML
- Introduction to IP Flow
- How to create XDC timing constraints
- Duration: 1 day online
- Time: 09:00 – 16:00 CET
- Spartan-6 users who want to migrate their existing design to the latest FPGA technology and are new to Vivado ML.
- FPGA designers who want to refresh their knowledge of XDC timing constraints. In addition to Clock and IO constraints, multicycle path, false path and other timing exceptions constraints are also discussed.
- 09:00 – 09:10 Introduction
- 09:10 – 09:35 Spartan-6 to Spartan-7 Architecture Migration– Guidance on migrating from Spartan-6 to other families – The architectural differences between the Spartan-6 and Spartan-7/Artix-7 – Some available resources to help guide people through the transition from ISE to Vivado
- 09:35 – 10:15 Introduction to Vivado ML Editions Tool FLow -Describe the various design flows in the Vivado Design Suite -Explain how the Vivado Tools flow is different from ISE tool flow -Identify and describe the supported use models in the Vivado Design Suite -What is a Netlist -How to create a project in Vivado ML and explain the different flow options -Briefly talk about IP Integrator and Vitis HLS
- 10:15 – 10:25 Break
- 10:25 – 10:45 Vivado ML Project Mode – Describe the project mode use model in the Vivado ML – Describe the structure and files of a project – Create a simple Vivado ML project in project mode
- 10:45 – 11:05 Synthesis and Implementation – This module describes the synthesis and implementation processes in the Vivado® IDE and the reports that are available after the process.
- 11:05 – 11:15 Break
- 11:15 – 11:30 Vivado IP Flow -This module describes the Vivado IP Flow , how to access IP from the IP catalog and describe the output files and synthesis flow
- 11:30 – 12:00 Introduction to XDC Clock Constraints – This module provides a brief introduction to clock constraint and their properties in the Vivado® Design Suite.
- 12:00 – 13:00 Break
- 13:00 – 13:20 Generated Clocks and Clock Groups -This module describes generated clocks in the Vivado® ML Editionsand introduces the application of clock group constraints that are used by the Vivado® timing engine to resolve timing issues.
- 13:20– 13:45 IO Constraints and Virtual Clocks – This module introduces how I/O timing constraints are made with the Vivado® IDE for single data rate applications
- 13:45– 13:55 Break
- 13:55 – 14:20 Setup and Hold Timing Analysis – This module covers the setup and hold timing analysis.
- 14:20 – 14:35 Timing Constraints Wizard – Use the Timing Constraints Wizard to create timing constraints – Validate the completion of timing constraints using Timing Constraints Wizard
- 14:35 – 14:45 Break
- 14:45 – 15:20 UltraFast Design Methodology Design Creation – This module introduces the design creation guidelines for the UltraFast™ Design Methodology
- 15:20- 15:45 Introduction to Timing Exceptions – This module introduces the application of multicycle paths, false paths, and max/min delay exception timing constraints.
- 15:45 – 15:55 Timing Constraints Priority – This module discusses the XDC precedence for timing exception constraints priority
- 15:55 – 16:00 Wrap-Up
30 September 2022
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