VHDL-2008 Features and Benefits
✅ indicates CONFIRMED TO RUN
- Date: Wednesday July 15, 2020
- Duration: 1 hour (with live Q&A)
- Time: 11am – 12pm (CEST)
- Presenter: Brian Jensen
- Cost: FREE!
The VHDL 2008 standard has been around since, well, 2009 actually. But despite the efforts of a few champions, the adoption of VHDL 2008 has taken some time. But things are improving! Simulation and synthesis support is now widespread.
In this webinar we review some of the many useful new features that were introduced with VHDL 2008, particularly focusing on the features that can be used by the most popular VHDL simulation and synthesis tools used in the FPGA design flow.
Learn about language features that make VHDL:
more convenient and easier to use
more powerful and expressive
more like Verilog!
and still portable between tools!
This webinar is particularly useful to you if you are considering the benefits of sticking with VHDL against perhaps moving towards a solution involving SystemVerilog.
Coding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on EDA Playground.
Doulos Senior Member Technical Staff Brian Jensen will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
15 July 2020