Webinar: Bug discovery by static code analysis

Free webinar Bug discovery by static code analysis

• Date: Thursday June 19, 2025
• Duration: 30min (with live Q&A)
• Time:
  
  • 11 - 11:30am (PDT) / 12 - 12:30pm (MDT)
  • 1 - 1:30pm (CDT) / 2 - 2:30pm (EDT)
  • 8 - 8:30pm (CEST)
• Presenter: Dr Reuven Dobkin
  
• Attendance: FREE!

Abstract:

RTL verification is one of the most time-consuming stages in the digital design cycle. Detecting bugs early can significantly shorten time-to-market and reduce overall design costs. Static analysis offers a powerful way to uncover many functional issues without the need for testbenches and dynamic simulations. In this webinar, we’ll demonstrate several common RTL bug patterns that can be automatically detected through static analysis, helping to achieve cleaner designs with full coverage.

If you have any queries, please contact info@vsyncc.com