Xilinx – Vivado HLS ONLINE
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
The course provides a thorough introduction to Vivado™ HLS (high-level synthesis). It covers:
- synthesis strategies
- improving throughput
- interface creation
- testbench coding
- coding tips.
You will learn how to utilize Vivado HLS to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.
This training also provides an essential background for developing Software Defined SoCs (find out more about Doulos SDSoC Adopter Training).
Who Should Attend?
Software and hardware engineers looking to utilize high-level synthesis.
Engineers looking to develop Software Defined SoCs (see SDSoC Adopter Training).
- C, C++, or System C knowledge
- High-level synthesis for software engineers OR high-level synthesis for hardware engineers
After completing this comprehensive training, you will know how to:
- Enhance productivity using Vivado HLS (high-level synthesis)
- Describe the high-level synthesis flow
- Use Vivado HLS for a first project
- Identify the importance of the testbench
- Use directives to improve performance and area and select RTL interfaces
- Identify common coding pitfalls as well as methods for improving code for RTL/hardware
- Perform system-level integration of blocks generated by Vivado HLS
Day 1 & 2
- Introduction to High-Level Synthesis and Vivado HLS
- Using Vivado HLS: GUI Flow
- Lab 1: Introduction to the Vivado HLS Tool Flow
- Vivado HLS Command Line Interface
- Lab 2 Introduction to the Vivado HLS CLI Flow
- Optimizing for Latency
- Lab 3: The Impact of Unrolling Loops
Day 3 & 4
- Optimizing for Throughput
- Lab 4: Optimizing for Throughput
- Optimizing Arrays
- Lab 5: Handling Memories
- Optimizing for Area
- I/O Interfaces
- Lab 6: Embedded System Integration
- Vivado HLS: C Code
- Lab 7: Matrix Multiplication
- Lab 1: Introduction to the Vivado HLS Tool Flow – Utilize the GUI to simulate and create a project. Perform RTL synthesis, verification, and exporting the C design as an IP.
- Lab 2 Introduction to the Vivado HLS CLI Flow – Utilize a make file to perform C simulation. Create a project and perform C synthesis, RTL verification, and RTL packaging.
- Lab 3: The Impact of Unrolling Loops – Analyze multiple results of the design and apply directives to optimize loop latency.
- Lab 4: Optimizing for Throughput – Optimize loop performance and modify pipelining and its affect on performance.
- Lab 5: Handling Memories – Analyze the impact of manipulating arrays. Utilize directives to optimize the design for area.
- Lab 6: Embedded System Integration – Set up an embedded design, create an HLS pcore to import into the embedded design, and validate the system on the demo board.
- Lab 7: Matrix Multiplication – Write a C-code 3×3 matrix multiplier, verify the design, and apply directives to improve performance.
09 december 2019 - 12 december 2019
Your home office
28 Xilinx Training Credits
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