Xilinx – Vivado FPGA Essentials ONLINE
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
This course will enable you to:
- build an effective FPGA design using synchronous design techniques
- instantiate appropriate device resources
- use proper HDL coding techniques
- make good pin assignments
- set basic XDC constraints
- use the Vivado Design Suite to build, synthesize, implement, and download a design.
Who Should Attend?
- Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
- Existing Xilinx ISE users who have no previous experience or training with the Xilinx PlanAhead suite and little or no knowledge of Kintex-7 or Virtex-7 devices.
- Engineers wishing to design with 6-series devices should contact Doulos for further information.
- Engineers who are already familiar with Xilinx 7-series devices and have at least some familiarity with PlanAhead should instead attend Vivado Design Suite. See the recommended learning path above and please contact Doulos for further information.
- Working HDL knowledge (VHDL or Verilog)
- Digital design experience
- Vivado System Edition 2015.3
- Architecture: 7 series FPGAs*
- Demo board: none
After completing this training, you will know how to:
- Take advantage of the primary 7 series FPGA architecture resources
- Use the Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
- Synthesize and implement an HDL design
- Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
- Build custom IP with the IP Library utility
- Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
- Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
- Describe and analyze common STA reports
- Identify synchronous design techniques
- Describe how an FPGA is configured.
Sessions 1 and 2
- Basic FPGA Architecture
- Vivado IDE Features and Benefits
- Introduction to the Vivado Design Suite
- Vivado IDE Project Manager and IP Library
- Vivado IDE Tool Overview
- Lab 1: Vivado Tool Overview
- Vivado IDE Synthesis and Reports
- Vivado IDE Implementation and Static Timing Analysis
- Lab 2: Vivado Synthesis and Implementation
Sessions 3 and 4
- Designing with FPGA Resources
- Clocking Resources
- Lab 3a: Designing with FPGA Resources
- Lab 3b: Creating an IP Integrator Subsystem Design
- Basic Timing Constraints (XDC)
- Timing Reports
- Lab 4: Basic XDC and Timing Reports
- Synchronous Design Techniques
- FPGA Configuration
- Course Summary
- Lab 1: Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
- Lab 2: Vivado Synthesis and Implementation – Synthesize and analyze the design with the Schematic viewer, review XDC timing constraints, and run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing critical paths with the Schematic viewer. Download the bitstream to the demonstration board.
- Lab 3a: Designing with FPGA Resources – use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks.
- Lab 3b: Creating an IP Integrator Subsystem Design – Use the IP Integrator to create a complex system design by instantiating and interconnecting IPs from the Vivado IP Catalog on a design canvas.
- Lab 4: Basic XDC and Timing Reports – Use the create_clock, set_input_delay, and set_output_delay timing constraints to improve design performance. Perform static timing analysis before and after implementation to validate the performance results.
02 mei 2017 - 05 mei 2017
Your home office
18 Xilinx Training Credits
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