Vivado Design Suite for ISE Software Project Navigator Users

Course Description

This course offers introductory training on the Vivado® Design Suite. This course is for experienced ISE® software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

vivado-flowLevel

FPGA 2

Course Duration

1 day

Who Should Attend?

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

Recommended Prerequisites

Software Tools

  • Vivado System Edition 2016.1

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize a systematic approach to apply timing constraints and achieve timing closure
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

  • UltraFast Design Methodology Introduction
  • Introduction to the Vivado Design Suite
  • Introduction to Vivado Design Flows
  • Vivado Design Suite Project-Based Flow
  • Vivado Design Suite Non-Project Mode
  • Lab 1: Vivado Design Suite Project-Based Flow
  • Vivado Design Suite I/O Pin Planning
  • Lab 2: Vivado Design Suite I/O Pin Planning
  • Demo: Basic Design Analysis in the Vivado IDE
  • Vivado IP Flow
  • Demo: Vivado IP Flow
  • Designing with IP Integrator
  • Demo: Designing with IP Integrator
  • Introduction to Clock Constraints
  • I/O Constraints and Virtual Clocks
  • Timing Constraints Wizard
  • Lab 3: Timing Constraints Wizard
  • Timing Constraints Editor
  • Introduction to Vivado Timing Reports
  • Synthesis and Implementation
  • Demo: Synthesis and Implementation Reports
  • Lab 4: Synthesis and Implementation

Lab Descriptions

  • Lab 1: Vivado Design Suite Project-Based Flow – Provides a basic overview of the project-based design flow and the simulation environment in the Vivado® Design Suite.
  • Lab 2: Vivado Design Suite I/O Pin Planning – Introduces the I/O pin planning capabilities of the Vivado Design Suite for FPGA devices.
  • Lab 3: Timing Constraints Wizard – Introduces the Timing Constraints Wizard which helps to create timing constraints in a design, such as clock and I/O constraints.
  • Lab 4: Synthesis and Implementation – Provides an overview of the process of synthesizing, implementating, and generating a bitstream.

 

Vivado


Datum
04 april 2017

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 750,00
of
9 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

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