Xilinx – Vivado Adopter Class ONLINE
|Whether you have designed with Xilinx devices before or not, this training program provides an optimized sequence of Vivado courses. Available as live instructor-led training online, it ensures you get the most out of your transition to the revolutionary IP and system-centric Vivado Design Suite just where you are.|
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
The sequence of Vivado courses in the Vivado Adopter ONLINE programe is shown in the following diagram, with different learning paths for NEW and EXISTING XILINX USERS. Select each course title for a detailed description.
To book a combination of Vivado courses please contact the Doulos sales team for assistance.
Summary course description:
The training uses materials developed by Xilinx, and conveniently combines:
- Vivado Design Suite
- Xilinx Vivado Advanced STA and XDC
- UltraFast Design Methodology
Who should attend?
- FPGA designers looking to utilize Vivado who:
- currently use the Xilinx ISE Design Suite
- already have some familiarity with Xilinx 7-Series devices
PLEASE NOTE: Engineers who are unfamiliar with Xilinx devices with no prior Xilinx ISE Design Suite experience should attend Vivado FPGA Essentials. This course provides new users a good grounding before attending more advanced training. See the learning path above and please contact Doulos for further information.
- FPGA design experience
- Intermediate VHDL or Verilog knowledge
- Completion of the Vivado FPGA Essentials or Essentials and Design for Performance and Advanced FPGA Implementation courses, or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques.
- Video Resources. The following videos contain essential content that will enable you to maximise the effectiveness of the Vivado training course:
- Essential viewing prior to course attendance:
- Optional viewing prior to course attendance:
- Essential viewing prior to course attendance:
Recommended additional training
- Essential Tcl for Vivado (online) teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado™ Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).
- Vivado System Edition 2015.3
Vivado Design Suite
- Use the Project Manager to start a new project
- Identify the Vivado IDE design flows (project based and non-project batch)
- Identify file sets (HDL, XDC, simulation)
- Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
- Synthesize and implement an HDL design
- Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
- Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
Xilinx Vivado Advanced XDC and STA
- Access primary objects from the design database and filter lists of objects using properties
- Describe setup and hold checks and describe the components of a timing report
- Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
- Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
- Describe all of the options available with the report_timing and report_timing_summary commands
- Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
- Analyze a timing report to identify how to center the clock in the data eye
- Create scripts for the project-based and non-project batch design flows.
UltraFast Design Methodology
- Describe the UltraFast Design Methodology Checklist
- Identify key areas to optimize your design to meet your design goals and performance objectives
- Define a properly constrained design
- Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
- Build resets into your system for optimum reliability and design speed
- Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
- Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
- Identify timing closure techniques using the Vivado Design Suite
- Describe how the Xilinx design methodology techniques work effectively through case study/lab experience
Structure and Content
VIVADO DESIGN SUITE
- Design Methodology Summary
- Vivado IDE Features and Benefits
- Introduction to the Vivado Design Suite
- Vivado IDE Project Manager and IP Library
- Vivado IDE Tool Overview
- Lab 1: Vivado Tool Overview
- Vivado IDE Synthesis and Reports
- Vivado IDE Implementation and Static Timing Analysis
- Lab 2: Vivado Synthesis and Implementation
- Appendix: SystemVerilog
- Appendix: Design Methodology
- Appendix: HDL Coding Techniques
XILINX VIVADO ADVANCED STA AND XDC
- Vivado IDE Review
- Accessing the Design Database
- Lab 3: Vivado IDE Database
- Static Timing Analysis and Clocks
- Lab 4: Vivado IDE Clocks
- Inputs and Outputs
- Timing Exceptions
- Lab 5: I/O and Timing Exceptions
- Advanced Timing Analysis
- Advanced I/O Interface Constraints
- Lab 6: Advanced I/O Timing
- Scripting Using Project-Based and Non-Project Batch Flows
- Lab 7a: Scripting in the Project-Based Flow
- Lab 7b: Scripting in the Non-Project Batch Flow
ULTRAFAST DESIGN METHODOLOGY
- Demo: UltraFast Design Methodology Checklist
- UltraFast Design Methodology
- HDL Coding Techniques
- Reset Methodology
- Lab 8: Resets
- Lab 9: SRL and DSP Inference
- Synchronization Circuits and the Clock Interaction Report
- Timing Closure
- UltraFast Design Methodology Case Study
- Demo: Performance Baselining
- Lab 10: Timing Closure and Design Conversion
- Course Summary
- Appendix: Timing Constraints Review
- Appendix: Synchronization Circuits and the Clock Interaction Report
- Appendix: Fanout and Logic Replication
- Appendix: Pipelining lab
- Lab 1: Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
- Lab 2: Vivado Synthesis and Implementation – Synthesize and analyze the design with the Schematic viewer, review XDC timing constraints, and run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing critical paths with the Schematic viewer. Download the bitstream to the demonstration board.
- Lab 3: Vivado IDE Database – Utilize the Vivado IDE database to set properties on a design.
- Lab 4: Vivado IDE Clocks – Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results.
- Lab 5: I/O and Timing Exceptions – Create I/O timing constraints for a source-synchronous design and make path-specific timing constraints and false path constraints with the Constraints viewer. Validate the system timing with the use of the timing reports available in the Vivado IDE.
- Lab 6: Advanced I/O Timing – Make I/O timing constraints for a source-synchronous, double data rate (DDR) interface. Perform a static timing analysis of the interfaces to determine the optimal clock and data relationship for maximum setup and hold-time margin. Finally, adjust the data path delay to realize the optimal timing solution.
- Lab 7a: Scripting in the Project-Based Flow – Write Tcl commands in the project-based flow for the design process (from creating a new project through implementation).
- Lab 7b: Scripting in the Non-Project Batch Flow – Write Tcl commands in the non-project batch flow for the design process (from creating a new project through implementation).
- Lab 8: Resets â€“ Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
- Lab 9: SRL and DSP Inference – Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.
- Lab 10: Timing Closure and Design Conversion – Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.
11 september 2017 - 15 september 2017
Your home office
31 Xilinx Training Credits
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