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Vitis Model Composer: A MATLAB and Simulink-based Product

 

Course Description

This course provides experience with using the Vitis™ Model Composer tool for modelbased designs.
The course provides experience with:

  • Creating a modelbased design using HDL, HLS, and AIE library blocks along with custom blocks in Vitis Model Composer
  • Implementing DSP functions using Vitis Model Composer
  • Utilizing design implementation tools
  • Transforming algorithmic specifications to productionquality IP implementations using automatic optimizations and leveraging the highlevel synthesis technology of the Vitis HLS tool
  • Creating Versal® AI Engine graphs and kernels using Vitis Model Composer
  • Connecting AI Engine blocks and nonAI Engine blocks
  • Verifying and debugging AI Engine code using the Vitis analyzer
  • Simulating and debugging a complex system created using AI Engine library blocks
  • Performing hardware validation using Vitis Model Composer

Leveldsp-sysgen

DSP 3

Course Duration

2 days

Audience

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB® and Simulink® software and want to use Vitis Model Composer

Prerequisites

  • Basic experience with the MATLAB and Simulink software
  • Basic understanding of DSP designs and sampling theory
  • Comfort with the C/C++ programming language for HLS or AI Engine model designs

 Software Tools

  • Vivado Design Suite 2023.1
  • Vitis unified software platform 2023.1
  • Vitis HLS tool 2023.1
  • MATLAB with Simulink software R2022a

 Hardware

  • Architecture: UltraScale™ FPGAs and Versal™ AI Core series*
  • Demo board: Zynq® UltraScale+™ MPSoC ZCU104 board*

* This course focuses on the UltraScale and Versal architectures. Check with your local Authorized Training Provider for the specifics of the inclass lab board or other customizations

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use optimized HDL, HLS, and AI Engine blocks directly from the Simulink tool library browser
  • Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using HDL, HLS, and AIE block libraries
  • Perform cosimulation and hardware verification
  • Use DSP blocks in Vitis Model Composer to implement DSP functions
  • Implement multirate systems in Vitis Model Composer
  • Design a processorcontrollable interface using Vitis Model Composer
  • Generate IPs from Cbased design sources using the Vitis HLS tool for use in the Vitis Model Composer environment
  • Import custom HDL, HLS, and AI Engines code as blocks into Vitis Model Composer
  • Generate output products using automatic code generation
  • Connect AI Engine blocks and nonAI Engine blocks
  • Perform AI Engine code verification using the Vitis analyzer
  • Create, simulate, and debug a complex system created using AI Engine library blocks
  • Validate an AI Engine design using hardware emulation

Course Outline

Day 1

  • Introduction to Vitis Model Composer – Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer. {Lecture}
  • Basics of the Simulink EnvironmentDescribes the Simulink software environment, some of the commonly used signal source and sink blocks available in the Simulink software, and how hierarchical designs are created and protected using masked subsystems. {Lecture, Lab} Vitis Model Composer for HDL
  • HDL Library in Vitis Model Composer – Illustrates how the HDL library can be used in Vitis Model Composer and how to analyze performance and resource usage in Vitis Model Composer. {Lecture, Lab}
  • HDL Library Compilation and Hardware CoSimulation – Covers how to import HDL modules as well as perform HDL cosimulation and hardware verification. Reviews the compilation types for Vitis Model Composer designs. Also introduces Super Sample Rate (SSR) blocks in Vitis Model Composer. {Lecture}
  • DSP Blocks in Vitis Model Composer – Describes the DSP blocks in the HDL and AI Engine library. Also reviews the basics of AXI4 interfaces. {Lecture, Lab}
  • Working with Filter DesignsDescribes the concept of designing filters supported by Vitis Model Composer. {Lecture, Lab}
  • Working with MultiRate SystemsExplains how a multirate DSP system uses multiple sampling rates within a system. {Lecture}

Day 2

  • HLS Library in Vitis Model ComposerDescribes how create Vitis Model Composer designs using HLS block libraries, import C/C++ code into Vitis Model Composer, and generate output products using automatic code generation. {Lecture, Labs}
  • AI Engine Library in Vitis Model ComposerDemonstrates the usage the AI Engine library in Vitis Model composer for creating an AI Engine design, which involves preparing the kernel and importing the AI Engine code as a block. {Lecture}
  • AI Engine Simulation and Code GenerationIllustrates the process of generating AI Engine code with a data flow graph, which involves Simulink simulation with the AI Engine library for functional verification. Also describe the hardware validation flow through generating a hardware image targeting a specific platform for the Simulink environment. {Lecture, Labs}
  • Connecting AI Engine and NonAI Engine Blocks – Explains how to interconnect AI Engine blocks and nonAI Engine (HDL and HLS) blocks. {Lecture}
  • Analyzing and Debugging an AI Engine Design in Vitis Model ComposerShows how to use the Vitis analyzer for viewing and analyzing various parameters that are useful for debugging Versal AI Engines. {Lecture, Lab}
  • Exploring Vitis Model Composer Examples in GitHubIntroduces different categories of Vitis Model Composer examples in GitHub and describes the methods to access these examples from GitHub. {Lecture}

 

DSP


Datum
19 februari 2024 - 20 februari 2024

Locatie
Core|Vision
Cereslaan 24
5384 VT
Heesch

Prijs
€ 0,00
of
20 Xilinx Training Credits

Informatie
Training brochure

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