VHDL for Designers ONLINE
Standard Level – 5 sessions CEST time: 10:00 – 14:00
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
How much VHDL training do you need? Watch the video now!
VHDL for Designers ONLINE prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC designers.
Uniquely, delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
The content of this course is identical to that of the face-to-face course VHDL for Designers (previously VHDL for FPGA Design). It uses the same agenda, presentation content, exercises/labs and supporting course materials (in electronic format).
Who should attend?
- Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
- Engineers who are about to embark on the first VHDL design project
- Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
What will you learn?
- The VHDL language concepts and constructs essential for FPGA design
- How to write VHDL for effective RTL synthesis
- How to target VHDL code to an FPGA device architecture
- How to write simple VHDL test benches
- The tool flow from VHDL through simulation, synthesis and place-and-route
- How to write high quality VHDL code that reflects best practice in the industry
No previous knowledge of VHDL or a software language is required. Delegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design.
Delegates preparing to design complex FPGAs or ASICs with VHDL may benefit from attending the following advanced training options from Doulos, specifically Advanced VHDL and Expert VHDL. This ONLINE course is a suitable pre-requisite for either of these classes.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include (in electronic format):
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos Golden Reference Guide for VHDL language, syntax, semantics and tips
- Design flow guide for ASIC and the leading FPGA/CPLD technologies
Because of enabling remote access on short order, demo boards cannot be shipped to customer addresses but it may be possible for delegates to use boards they already have access to locally. However remote access is provided to appropriate simulation and synthesis tools supporting the FPGA design flow.
Note: the learning outcomes are not primarily dependent on delegates having access to suitable demo boards
Structure and Content
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
FPGA Design Flow (Practical exercises using a hardware board)
Simulation • Synthesis • Place-and-Route • Device programming
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
Synthesising Combinational Logic
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Synthesis of Arithmetic
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
Synthesising Sequential Logic
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO
21 januari 2019 - 25 januari 2019
Your home office
42 Xilinx Training Credits
Registratie op aanvraag, neem contact op met ons.