VHDL for Designers

Course Description

VHDL for Designers (Xilinx) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module.
Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.

What will you learn?compvhdl_learningpath

VHDL for Designers

  • The VHDL language concepts and constructs essential for FPGA design
  • How to write VHDL for effective RTL synthesis
  • How to target VHDL code to an FPGA device architecture
  • How to write simple VHDL test benches
  • The tool flow from VHDL through simulation, synthesis and place-and-route
  • How to write high quality VHDL code that reflects best practice in the industry

Pre-requisites

Delegates must have attended Essential Digital Design Techniques or an equivalent course, or have a good working knowledge of digital hardware design. No previous knowledge of VHDL or a software language is required.

Delegates attending only the Advanced VHDL module must have some hardware design experience, and have completed the VHDL for Designers module or an equivalent course. We have found that delegates frequently overestimate their own capabilities. If in doubt, you will probably benefit from attending the full Comprehensive VHDL course.

Course materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:

  • Fully indexed course notes creating a complete reference manual
  • Workbook full of practical examples to help you apply your knowledge
  • Doulos Golden Reference Guide for VHDL language, syntax, semantics and tips
  • Tool tour guides (to support the tools and technologies of your choice)
  • Design flow guide for ASIC and the leading FPGA/CPLD technologies

Doulos


Datum
11 maart 2019 - 13 maart 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 2.695,00
of
42 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

VHDL for Designers Doulos-11000

€ 2.695,00