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TZID:Europe/Amsterdam
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BEGIN:VEVENT
UID:1164@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260420T090000
DTEND;TZID=Europe/Amsterdam:20260421T170000
DTSTAMP:20260325T110431Z
URL:https://www.core-vision.nl/events/ultrascale-designing-with-the-sparta
 n-ultrascale-fpga-architecture-4/
SUMMARY:UltraScale+ Designing with the Spartan UltraScale+ FPGA: Architectu
 re
DESCRIPTION:Course Description\nLearn about the key features and architectu
 re of the AMD Spartan™ UltraScale+™ FPGA\, including its advanced I/O\
 , high-speed transceivers\, substantial built-in and external memory\, PCI
 e® Gen4 connectivity\, and modern security. Recognize how these features 
 provide a versatile\, cost-optimized\, and power-efficient platform for di
 verse applications.\nThe emphasis of this course is on:\n\n 	Describing th
 e key features and fundamental blocks of the Spartan UltraScale+ FPGA arch
 itecture\n 	Describing Spartan UltraScale+ clocking\, including buffer typ
 es\, clock management tiles\, and routing for enhanced timing\n 	Describin
 g the various on-chip memory resources available in the Spartan UltraScale
 + architecture\n 	Utilizing the advanced I/O capabilities for various conn
 ectivity needs\n 	Identifying the high-speed transceivers for use in appli
 cations such as PCIe Gen4\n 	Explaining the configuration process for Spar
 tan UltraScale+ devices\n 	Outlining the platform security framework and a
 dvanced security features\n 	Leveraging the Power Design Manager (PDM) too
 l for power estimation\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 25/12/Spartan-UltraScale-right-angle-tiltedx526-e1764594111485.png
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
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DTSTART:20260329T030000
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