UltraFast Design Methodology

Course Description

This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Level

FPGA 3

Training Duration

2 days

Audience

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Prerequisites

• Basic HDL knowledge (VHDL or Verilog)
• Digital design knowledge and experience
• Vivado Design Suite experience or completion of either:
  • Designing FPGAs Using the Vivado Design Suite 1 course and
  • Designing FPGAs Using the Vivado Design Suite 2 course and
  • Designing FPGAs Using the Vivado Design Suite 3 course or
  • Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users course

Software Tools

• Vivado Design or System Edition 2019.1

Hardware

• Architecture: UltraScale™ and 7 series FPGAs*

Demo board: None*

* This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe the UltraFast™ design methodology checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the UltraFast design methodology techniques work effectively through case studies and lab experience

Course Outline

Day 1

• UltraFast Design Methodology: Introduction – Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist. {Lecture, Demo}
• UltraFast Design Methodology: Board and Device Planning – Introduces the methodology guidelines on board and device planning. {Lecture}
• Vivado Design Suite I/O Pin Planning – Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}
• Xilinx Power Estimator Spreadsheet – Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}
• Introduction to FPGA Configuration – Describes howFPGAs can be configured. {Lecture}
• UltraFast Design Methodology: Design Creation – Introduces the UltraFast methodology guidelines on design creation. {Lecture}
• HDL Coding Techniques – Covers basic digital coding guidelines used in an FPGA design. {Lecture}
• Resets – Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
• Register Duplication – Use register duplication to reduce high fanout nets in a design. {Lecture}
• Pipelining – Use pipelining to improve design performance. {Lecture, Lab}
• Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design. {Lecture}
• Creating and Packaging Custom IP – Create your own IP and package and include it in the Vivado IP catalog. {Lecture}