Solving Clock Domain Crossover Conflicts

Course Description

Vincent Platform

FPGA and ASIC designs often suffer from Clock Domain Crossover conflicts.Certain discipline and or using structuring blocks will prevent most of the problems however with increased complexity and scaling to smaller nodes flawlessly designing becomes a true challenge and time spent on it is increasing rapidly. Proper training and tools can save a large amount of precious engineering time.

Training Duration

2  days

Who Should Attend?

ASIC/FPGA designers who would like to solve their Clock Domain Crossing issues

Course Outline

DAY 1

Multiple Clock Domain Designs
  • Single vs. Multiple clock domains
  • Clock distribution
  • Clock gating and low power
  • DVFS systems
Metastability
  • Theory behind Metastability
  • Physical simulation of Metastability
  • Physical behavior and Metastability resolution
Mean Time Between Failure
  • Metastability handling approaches
  • Two-Flops synchronizer
  • System reliability
  • MTBF and operating conditions (commercial, industrial, military)
  • Improving Metastability in ASIC/FPGA
Synchronization & Common Mistakes
  • Synchronizaers & Protocols
  • Control and data validity
  • Common synchronization mistakes
  • Bug production
Standard Synchronizers
  • Synchronizer requirements
  • Mesochronous synchronizers
  • Asynchronous synchronizers
  • Two-Clock FIFO
  • Reset synchronization
  • Performance and trade-offs in synchronizers
  • FPGA clock distribution and PLLs
  • Data transfer between related clocks
 
Advanced Topics on Synchronization
  • GALS systems
  • vSync Vincent CDC platform
  • MTBF of correlated clocks.

Day 2

Clock Distribution Networks
  • Problem definition
  • What’s Ahead: The technology Roadmap
  • ASIC/SoC vs. Full-Custom Design Methodologies
  • Standard Clock Trees for SoC’s and FPGA
  • Min-Delay and Max-Delay Problems
  • Data Delay Insertion and Delay Line Circuits
  • Clock Delay Insertion and Clock Tuning
  • Unbalanced Tuneable Clock Distribution Networks
  • High Performance Clock Trees
  • Local Clock Generation with Tuneable Frequencies
Measuring Metastability
Coherent Clock Analysis
Advanced topics on Asynchronous Synchronizers
  • Pulse synchronizer
  • A practical implementation of a 2-clock Gray-code FIFO
  • Reset, Clear and Clock Switching (active / non-active clocks)
  • Mutual Exclusion and Arbiters
  • 2-Flop Synchronizer simulation model
  • X-propagation
Multi-Synchronous and Periodic Synchronizers
  • Mesochronous/Multi-Sync Synchronization
  • Delay Variations
  • Data Delay Synchronizers
  • Conflict Detection
  • Clock Delay Synchronizers
  • FIFO Synchronizers
  • Clock Edge Synchronizers
  • Periodic Domains and Predictive Synchronizers
Multi-Clock Domain and GALS SoC
  • Synchronizer-based GALS
  • Arbitrated and Handshake Stoppable Clocks
  • Wrappers and Asynchronous Ports
  • GALS Methodologies
  • Synchronization in Networks on Chips (NoC)

vSync Circuits


Datum
08 april 2019 - 09 april 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.795,00

Registratieformulier

VSYNC-2D

€ 1.795,00