Rule policy for IP design

indicates CONFIRMED TO RUN

  • Date: Wednesday December 20 2023
  • Duration: 30min (with live Q&A)
  • Time: 11:00 – 11:30 (CEST)
  • Presenter: Dr Reuven Dobkin
  • Attendance: FREE!

 

Webinar Overview

Multiple companies develop IP modules for ASIC and FPGA designs. The IP modules should be clean of functional bugs to avoid multiple iterations between the IP providers and their customers. In addition, the IP modules must be generic enough to support different target ASIC/FPGA technologies. During this webinar, we will review IP design requirements and exemplify how these requirements can be automatically verified using LINT tools.

 

If you have any queries, please contact info@vsyncc.com

vSync Circuits


Date
20 December 2023

Location
Webinar
Online

Webinar

Price
€ 0,00

Information
Training brochure

Registration form

Registration on demand, please contact us.