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TZID:Europe/Amsterdam
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UID:1217@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260921T090000
DTEND;TZID=Europe/Amsterdam:20260924T170000
DTSTAMP:20260408T130005Z
URL:https://www.core-vision.nl/events/python-cocotb/
SUMMARY:IC Verification with Python and cocotb
DESCRIPTION:Course Description\nIC Verification with Python and cocotb is a
  4 days class that teaches how to use coroutine based co-simulation testbe
 nch (cocotb)\, a Python-based simulation environment\, to carry out RTL ve
 rification.\n\nPython is pervasive: often taught as a first programming la
 nguage in most STEM degree courses. This course is an attractive option fo
 r verification engineers to accelerate their project-readiness by using Py
 thon instead of learning a new hardware verification language\, such as Sy
 stemVerilog.\n\nPython’s use in semiconductor design and verification ex
 tends from scripting for data pre-processing/post processing\, flow contro
 l\, through to verification test case development and “on the fly” che
 cking.\n\nPython also has a very rich ecosystem of utility libraries that 
 can be leveraged to accelerate development of verification test benches an
 d domain specific verification IP for ASIC/SOC/FPGA projects. Covering suc
 h areas as: digital signal processing for audio &amp\; vision pipelines as
  well as most aspects of Machine Learning. Often\, projects are using the 
 same generators &amp\; checkers in the hardware algorithm system modelling
  as in the RTL design-under-verification.\n\nPython serves as a common bas
 eline for teams composed of different engineering disciplines.\n\nFurtherm
 ore\, Python is a cost-effective way to extend a team’s scope without th
 e need for significant investment to re-skill on a new set of programming 
 languages.\n\nIn this course:\n\n 	FPGA is set as the primary context - ho
 wever all the concepts can be equally applied to IP/ASIC/SOC target design
 s.\n 	The verification target is assumed to be written in VHDL - however a
 ll concepts can be equally applied to Verilog/SystemVerilog.\n\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 26/04/coctb-core-vision.jpg
CATEGORIES:Cocotb,Doulos
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
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 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
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TZID:Europe/Amsterdam
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DTSTART:20260329T030000
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