IC Verification with Python and cocotb

IC Verification with Python and cocotb

When

21 september 2026 - 24 september 2026     
09:00 - 17:00

Reserve

€3.295,00
 / 51  Training Credits
On request

Where

Core-Vision
Cereslaan 24, 5384 VT, Heesch
Nederland

Event type

Information

Kaart niet beschikbaar

Course Description

IC Verification with Python and cocotb is a 4 days class that teaches how to use coroutine based co-simulation testbench (cocotb), a Python-based simulation environment, to carry out RTL verification.

Python is pervasive: often taught as a first programming language in most STEM degree courses. This course is an attractive option for verification engineers to accelerate their project-readiness by using Python instead of learning a new hardware verification language, such as SystemVerilog.

Python’s use in semiconductor design and verification extends from scripting for data pre-processing/post processing, flow control, through to verification test case development and “on the fly” checking.

Python also has a very rich ecosystem of utility libraries that can be leveraged to accelerate development of verification test benches and domain specific verification IP for ASIC/SOC/FPGA projects. Covering such areas as: digital signal processing for audio & vision pipelines as well as most aspects of Machine Learning. Often, projects are using the same generators & checkers in the hardware algorithm system modelling as in the RTL design-under-verification.

Python serves as a common baseline for teams composed of different engineering disciplines.

Furthermore, Python is a cost-effective way to extend a team’s scope without the need for significant investment to re-skill on a new set of programming languages.

In this course:

  • FPGA is set as the primary context - however all the concepts can be equally applied to IP/ASIC/SOC target designs.
  • The verification target is assumed to be written in VHDL - however all concepts can be equally applied to Verilog/SystemVerilog.


Audience

Engineers with a need to verify FPGA/ASIC/Hardware IP designs, or who wish to rapidly upskill on efficient and effective verification techniques based on the cocotb Python framework, bypassing the need for ramping up on another hardware verification language (HVL) such as SystemVerilog and associated frameworks such as UVM.

What will you learn?

  • Hardware verification principles
  • Key Python language features
  • cocotb principles
  • How to construct the different aspects of a verification environment using cocotb.
  • Verification strategies and tactics covering: directed tests, bottom up vs top down, use of stubs, partitioning the Test Bench between Python and RTL, debugging and constrained random
  • Making use of 3rd party packages for verification

Pre-requisites

Basic knowledge and experience of Python programming is desirable but not necessary as the course covers the Python language features that are needed.

A foundational knowledge of  digital hardware design (as covered by Doulos’ Essential Digital Design Techniques course) would be beneficial but not essential.

Training materials

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique and has made them sought after resources in their own right. The materials include:

  • Fully indexed class notes creating a complete reference manual
  • A workbook full of practical examples and solutions to help you apply your knowledge.

Request

Tickets

VERIF-PYTH-COCO

€3.295,00

Registration information

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