Maximize Design Productivity using Vivado ML with SystemVerilog

indicates CONFIRMED TO RUN

 

Register Now

 

  • Date: Wednesday  September 20, 2023
  • Duration: 1 hour (with live Q&A)
  • Time: 11am – 12pm
  • Presenter: Mike Smith
  • Cost: FREE!

Webinar Overview:

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using Vivado™ ML Editions from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

We start from the basic principles of RTL coding style in SystemVerilog, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls.

Content Summary:

  • Introduction
  • SystemVerilog in the Vivado Design Suite
  • Modules, ports, parameters, and hierarchy
  • Testbenches
  • Combinational and clocked logic
  • Assignments and procedures
  • Control constructs and operators
  • Hardware-oriented data types including packages
  • Interfaces and Modports

Mike Smith – Doulos Certified Training Instructor, will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Attendance is free of charge

Doulos


Date
20 September 2023

Location
Webinar
Online

Webinar

Price
€ 0,00

Information
Training brochure