Integrating the Arm Cortex-M3 in a Xilinx FPGA
✅ indicates CONFIRMED TO RUN
- Date: Friday 16 October 16, 2020
- Duration: 1 hour (with live Q&A)
- Time: 11am – 12pm (CEST)
- Presenter: Dr David Cabanis
- Cost: FREE!
A best-of-both worlds solution for embedded systems
The combination of the widely acclaimed Arm® Cortex®-M MCU architecture with the performance of a Xilinx® FPGA provides more flexibility and greater scope for innovation in the creation of application-optimised designs.
Many Vivado® users are familiar with the Microblaze™ RISC processor. However, the Arm Cortex-M3 has a substantially different hardware architecture, with unique system integration aspects.
In this webinar we will examine the Cortex-M3 IP block and discuss its integration inside a Xilinx FPGA.
- Examine the two main system busses, their use model and restrictions
- Review the operations of the Nested Vectored Interrupt Controller (NVIC) and its interaction with a Wakeup Interrupt Controller (WIC)
- Examine the memory management operations along with invasive and non-invasive debugging features of the core.
Dr David Cabanis Doulos Principal Member Technical Staff and Arm certified expert, will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.
Attendance is free of charge
16 October 2020