High-Level Synthesis with the Vitis HLS Tool

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Course Description

This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool. The focus is on:

• Converting C/C++ designs into RTL implementations
• Learning the Vitis HLS tool flow
• Creating I/O interfaces for designs by using the Vitis HLS tool
• Applying different optimization techniques
• Improving throughput, area, latency, and logic by using different HLS pragmas/directives
• Exporting IP that can be used with the Vivado® IP catalog
• Downloading for in–circuit validation

Level

DSP 3

Course Duration

2 days

Audience

Software and hardware engineers looking to utilize high-level synthesis

Prerequisites

• C, C++, or System C knowledge
• High-level synthesis for software engineers OR high-level synthesis for hardware engineers

Software Tools

• Vitis HLS tool 2022.2
• Vivado Design Suite 2022.2
• Vitis unified software platform 2022.2

Hardware

• Architecture: Zynq® UltraScale+™ MPSoC and Versal® AI Core series*
• Demo board: ZynqUltraScale+ MPSoC ZCU104 board*

* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations

Skills Gained

After completing this comprehensive training, you will know how to:

• Enhance productivity by using the Vivado HLS tool
• Describe the high-level synthesis flow
• Use the Vivado tool HLS for a first project
• Identify the importance of the testbench
• Use directives to improve performance and area and select RTL interfaces
• Identify common coding pitfalls as well as methods for improving code for RTL/hardware
• Perform system-level integration of IP generated by the Vivado HLS tool

Course Outline

Day 1

• Introduction to High-Level Synthesis – Overview of the High-level Synthesis (HLS), Vitis HLS tool flow, and the verification advantage. {Lecture}
• Vitis HLS Tool Flow – Explore the basics of high-level synthesis and the Vitis HLS tool. {Lecture, Demo, Lab}
• Abstract Parallel Programming Model for HLS – Describes the structuring of a design at a high level using anabstract parallel programming model. {Lecture}
• Design Exploration with Directives – Explore different optimization techniques that can improve the design performance. {Lecture}
• Vivado HLS Tool Command Line Interface – Describes the Vitis HLS tool flow in command prompt mode. {Lecture, Lab}
• Introduction to HLS UltraFast Design Methodology – Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps. {Lecture}
• Introduction to I/O Interfaces – Explains interfaces such as block-level and port-level protocols abstracted by the Vitis HLS tool from the C design. {Lecture}
• Block-Level I/O Protocols – Explains the different types of block-level protocols abstracted by the Vitis HLS tool. {Lecture, Lab}
• Port-Level I/O Protocols – Describes the port-level interface protocols abstracted by the Vitis HLS tool from the C design. {Lecture, Demo, Lab}
• AXI4 Adapter Interface Protocols – Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS tool. {Lecture, Demo}
• Port-Level I/O Protocols: Memory Interfaces – Describes the memory interface port-level protocols (such as block RAM, FIFO) abstracted by the Vitis HLS tool from the C design. {Lecture, Lab}
• Pipeline for Performance: PIPELINE – Describes the PIPELINE directive for improving the throughput of a design. {Lecture, Lab}

Day 2

• Pipeline for Performance: DATAFLOW – Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. {Lecture, Lab}
• Optimizing for Throughput – Identify the performance limitations caused by arrays in your design. You will also explore optimization techniques to handle arrays for improving performance. {Lecture, Demo, Lab}
• Optimizing for Latency: Default Behavior  – Describes the default behavior of the Vitis HLS tool on latency and throughput. {Lecture}
• Optimizing for Latency: Reducing Latency – Describes how to optimize the C design to improve latency. {Lecture}
• Optimizing for Area and Logic – Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. {Lecture, Lab}
• Migrating to the Vitis HLS Tool  – Reviews key considerations when moving from the Vivado HLS tool to the Vitis HLS tool. {Lecture}
• HLS Design Flow – System Integration – Describes the traditional RTL flow versus the Vitis HLS design flow. {Lecture, Lab}
• Vivado HLS Tool C++ Libraries: Arbitrary Precision – Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types. {Lecture, Lab}
• Hardware Modeling – Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class. {Lecture}
• Using Pointers in the Vivado HLS Tool – Explains the use of pointers in the design and workarounds for some of the limitations. {Lecture}