Free Versal Adaptive SoCs: Network on Chip ONLINE WORKSHOP
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The Versal® adaptive SoC from AMD is multi-featured, offering unprecedented system level performance and integration.
This workshop (delivered in 2 half day sessions) introduces the Versal™ adaptive SoC Network on Chip (NoC).
Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The workshop is designed to maximize individual engagement and learning.
Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process.
2 half day sessions
Audience & Pre-requisitis
Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal adaptive SoC.
This workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A.
- Each session duration is up to 5 hours including breaks
- Start times:
- Europe and Asia Time Zones:
0830 BST | 0930 CEST | 1300 India (IST)
- Americas Time Zones:
0830 PDT | 1030 CDT | 1130 EDT
- Europe and Asia Time Zones:
- There are no specific hardware requirements for this training please check your connection with GoToWebinar if you have not used it to attend a Doulos event before.
- Architecture Overview for Existing Xilinx Users – Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices.
- Versal ACAPs Compared to Zynq UltraScale+ Devices – The Versal ACAP has a number of similarities to the Zynq® UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context.
- NoC Introduction and Concepts – Reviews the basic vocabulary and high–level operations of the NoC.
- NoC Architecture – Provides the first deep dive into the sub–blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic.
- Design Tool Flow Overview – Designers come to the Versal ACAP devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the Xilinx toolbox.
- NoC DDR Memory Controller – The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC’s DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use.
- NoC Performance Tuning – Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance.
- System Design Migration – Describes how different users will leverage tools and processes to migrate their designs to the Versal ACAP devices.
Versal Adaptive SoC: Network on Chip Workshop Schedule – June 2023
Register using a link below for FREE
June 29-30 2023 – Americas – Register now »
June 29-30 2023 – EurAsia – Register now »
29 juni 2023 - 30 juni 2023